Stories
Slash Boxes
Comments
Search

News for nerds, stuff that matters

Slashdot Log In

Log In

Create Account  |  Retrieve Password

Chip Power Breakthrough Reported by Startup

Posted by ScuttleMonkey on Mon May 08, 2006 05:29 PM
from the processor-still-suit dept.
Power Technology
Carl Bialik from WSJ writes "The Wall Street Journal reports that a tiny Silicon Valley firm, Multigig, is proposing a novel way to synchronize the operations of computer chips, addressing power-consumption problems facing the semiconductor industry. From the article: 'John Wood, a British engineer who founded Multigig in 2000, devised an approach that involves sending electrical signals around square loop structures, said Haris Basit, Multigig's chief operating officer. The regular rotation works like the tick of a conventional clock, while most of the electrical power is recycled, he said. The technology can achieve 75% power savings over conventional clocking approaches, the company says.'"
+ -
story
This discussion has been archived. No new comments can be posted.
The Fine Print: The following comments are owned by whoever posted them. We are not responsible for them in any way.

Chip Power Breakthrough Reported by Startup 50 Comments More /

 Full
 Abbreviated
 Hidden
More
Loading... please wait.

  • Article text for the hard-of-linking (Score:3, Informative)

    by Anonymous Coward on Monday May 08 2006, @05:31PM (#15288910)
    Chip Power Breakthrough Reported
    By DON CLARK
    May 8, 2006; Page B6

    A tiny Silicon Valley company is proposing a novel way to synchronize the operations of computer chips, addressing power-consumption problems that are a major issue facing the semiconductor industry.

    Multigig Inc., a closely held start-up company in Scotts Valley, Calif., says its technology is a major advance over the clock circuitry used on many kinds of chips.

    Semiconductor clocks work like the drum major in a marching band, sending out electrical pulses to keep tiny components on chips performing operations at the right time. In microprocessor chips used in computers, the frequency of those pulses -- also called clock speed -- helps determine how much computing work gets done per second.

    One problem is that the energy from timing pulses flows in a one-way pattern through a chip until it is discharged, wasting most of the power. Clocks account for 50% or more of the power consumption on some chips, estimates Kenneth Pedrotti, an associate professor of electrical engineering at the University of California at Santa Cruz.

    Partly for that reason, companies such as Intel Corp. have all but stopped increasing the clock speeds of microprocessors, a popular way to increase computing performance through most of the 1990s.

    John Wood, a British engineer who founded Multigig in 2000, devised an approach that involves sending electrical signals around square loop structures, said Haris Basit, Multigig's chief operating officer. The regular rotation works like the tick of a conventional clock, while most of the electrical power is recycled, he said. The technology can achieve 75% power savings over conventional clocking approaches, the company says.

    A typical chip would use an array of timing loops, in a grid akin to a piece of graph paper, Mr. Basit said. The loops automatically synchronize their timing pulses. That feature helps address a problem called "skew" -- the slightly different arrival times of timing pulses throughout a typical chip -- that tends to limit clock precision.

    Multigig says its self-synchronizing loops can run efficiently at unusually high frequencies.

    Mr. Pedrotti said past attempts to address the skew problem have tended to increase power consumption. He and his students, some of whom receive research funding from Multigig, have performed simulations that so far back up the company's claims, though the team is just about to start tests using actual chips, he said.

    Multigig is in talks to license its technology to chip makers, as well as design some of its own products to use the clock technology. Besides microprocessors and other digital chips, the approach could help synchronize frequencies of communication chips, Mr. Basit said.

    "This is a dramatic way of clocking circuits," said Steve Ohr, an analyst at Gartner Inc. He cautioned it could take years to get existing manufacturers to modify existing products to take advantage of the new technology. "Intel is not going to redesign the Pentium tomorrow because of it," he said.

      • Re:I'll call bullshit (Score:4, Interesting)

        by rufty_tufty (888596) on Tuesday May 09 2006, @07:08AM (#15292087)
        Clock skew impacts your timing margin (If you've got 2 flip flops that in theory see the clock at the same instant, any uncertainty in the clock arriving will inpact your timing from one to the other). One concequence of this is you often have to have larger faster drivers on both your clock tree and your logic to work around this timing problem.
        Larger drivers = larger power.

        Therefore if you've got a method to make your clocks arrive more accuratly then you've more timing margin between FFs and therfore can use smaller drivers.

        Clock trees are also the major consumer of power in most designs, so anything that can reduce them is good.

        Async removes the clock altogether so you save power there.

        So yes both of them can be right.

  • This is a breakthrough! (Score:4, Funny)

    by Anonymous Coward on Monday May 08 2006, @05:34PM (#15288924)
    Conventional electronics uses circular loop structures to send electrical signals as the electrons would get caught on corners that were too sharp. These people must have overcome that limitation.
    • Conventional chip makers use EVIL CIRCULAR electron path. Embrace SQUARE CIRCUITS and escape EVIL and DUMB circular technology. Then you will realize that electrons travel on FOUR SIMULTANEOUS ORBITS on their way through a microchip.

    • not far off (Score:3, Informative)

      by nomel (244635)
      actually...sharp turns are a problem for high frequency circuits. when the frequencies get very high compared to the wires length, the waves *do* actually reflect back from sharp corners and will favor a straight path. this is the basis for things such as tdr (when finding kinks) and directional couplers.

  • Simple Math (Score:4, Informative)

    by Ossifer (703813) on Monday May 08 2006, @05:35PM (#15288928)
    So "up to" 75% savings on "up to" 50% of the electricity usage. So 3/8 or 37.5% savings, all in all... Of course this is only for the CPU... Could be noticeable in production... Maybe...
    • So "up to" 75% savings on "up to" 50% of the electricity usage. So 3/8 or 37.5% savings, all in all...
      If it saves that much electricity on the CPU, that should also yield a heat reduction.

      Now, whether it is linear or not, any heat reduction is a Good Thing (tm).

      Hopefully we can choose between faster chips at the heat levels we have now, or the same speed chips at a 37.5% reduction in heat (and points in between).
    • In your average laptop, the power consumed by a CPU when running something (i.e. not just idling around) is about half the total power. The other half, roughly, is consumed by the screen.

    • Advertising lingo - "up to" (Score:4, Insightful)

      by Weaselmancer (533834) on Monday May 08 2006, @07:42PM (#15289489)

      Remember, in advertising-speak, "up to" means "less than". Values between 0% and 75% fulfill the conditions of being "up to a 75% savings".

  • Getting closer (Score:3, Funny)

    by From A Far Away Land (930780) on Monday May 08 2006, @05:39PM (#15288947) Homepage Journal
    We're getting ever closer to the perpetual motion machine, just 25% energy savings to go ;-)

    Seriously though, I'll look forward to seeing this new chip in production, since more energy efficient chips means less waste heat, and thus quieter computers with fewer fans. I'll trust it when I see it, I'm not so swayed by a company that is still just a "startup" probably looking to get a boost to its stock price by anouncing a breakthrough.

  • You might save a lot of power (Score:2, Informative)

    by Anonymous Coward
    Most of the power in a computer is used once and wasted. The input to a gate acts like a capacitor. When the input is driven from a zero to a one, the current is limited by the resistance of the output gate driving it. That resistance is where the power is dissipated. The charge is drained to ground when the input is driven from a one to a zero. If there was some way to re-use the charge stored in the inputs, the power dissipation of a chip could be dramatically reduced. There would be a limit to how

  • No overclocking (Score:3, Interesting)

    by rcw-work (30090) on Monday May 08 2006, @05:49PM (#15288987)
    You can't readily adjust the amount of time it takes electricity to make its way around a fixed-size loop. If this is what is actually clocking the chip, it'll have an official frequency (or two, perhaps, for low-power usage) and you'll be stuck with that. The manufacturer would have to throw out, rather than derate, any parts that don't work at that frequency.
    • Not necessarily. That just sets a lower bound (of sorts) on the performance.

      You're assuming that A. there can be only one pulse in flight at a time (which is probably not the case) and B. that the breadth of the pulse is constant. I would expect that in such a design, calculation might occur on the rise and the value would be propagated to the next stage of the CPU on the fall, which would mean that the pulse width and number of concurrent pulses in the loop could be adjusted to allow for significant va

      • You can put a harmonic on the loop, but it needs to be in phase with the wavelength of the loop, which limits you to integer harmonics, and there are practical upper limits to the harmonics you can cheaply use. I don't think they'd ship a chip that had, say, a 500MHz loop and use a 20x harmonic to get 10GHz, so that as a user, you could select 21x or 22x instead. I think it'd be more likely that for the 10GHz example, they'd give you a CPU with a 3.3GHz loop. You'd get the rated 10GHz frequency, and 3.3GHz

  • Sounds good but what about size? (Score:4, Insightful)

    by mustafap (452510) on Monday May 08 2006, @05:51PM (#15288995)
    Like with asynchronous processors, maybe its downside will be the silicon area required to implement it.

    Other techniques like multiple independant clock areas that can be shut down when not in use seem far more beneficial, IMHO.

  • vaporware...? (Score:5, Insightful)

    by moochfish (822730) on Monday May 08 2006, @05:54PM (#15289019)
    It just amazes me that a small, never-before-heard-of-company offers a solution to a problem that Intel, IBM, and AMD have been trying to solve for over a decade, each of which have 10 times the budget, expertise, and personel. Did I mention a headstart of a minimum of 10 years of R&D tossed at this problem? I hate to be a pessimistic troll-like poster, but without even a working proof of concept, I can only call this vaporware until they show me a working product. This article says nothing except "we have technology every computer in the world will need in the next ten years... please invest in us and we'll get you a demo soon."

    • Re:vaporware...? (Score:4, Insightful)

      by Jeremi (14640) on Monday May 08 2006, @10:22PM (#15290322) Homepage
      It just amazes me that a small, never-before-heard-of-company offers a solution to a problem that Intel, IBM, and AMD have been trying to solve for over a decade, each of which have 10 times the budget, expertise, and personel.


      I'm in no way qualified to comment on the actual technology here, but I will submit that this situation isn't as unlikely as it might seem. For many problems, the potential solution-space is so large (and the cost of trying out various approaches is so significant) that even a large R&D lab with a big budget and years of effort can end up missing what in retrospect is a very clever and useful solution. It's easy to get bogged down trying "just one more tweak" of your first (or second or third) approach that you never look around and notice the other approach hiding in plain sight. Even worse, a given organization can easily build up a culture that says "this is the way we do things, because this is the way we know things work", which can discourage even bright new employees from looking at alternative methods. (i.e. Why "start from scratch" with approach B when your company has invested millions in developing approach A?)


      A new startup, on the other hand, doesn't have all that baggage that might limit their point of view. Or even more likely, some bright person may have had The Big Idea, and decided to found a startup to exploit it and get rich, rather than donating his idea to some pre-existing corporation.


      That said, there is plenty of room for bullshit vaporware in the world too :^)

  • An impossible concept only invented like a hundred years ago. Next, they will be charging things known as capacitors from the induced current.

  • I call BS (Score:5, Insightful)

    by Avian visitor (257765) on Monday May 08 2006, @06:16PM (#15289124) Homepage
    I've read the FA and despite having a couple of CMOS designs behind me I don't understand a bit of what they are saying. Either the reporter that wrote this has absolutely no idea what he is writing or this entire 'breaktrough' is just vapourware.

    The article seems to say that the 'tick' of the clock is carrying energy throughout the chip and when the 'tick' hits the edge, the energy is lost. Electronics in your typical digital circuit does not work that way. Energy does not flow through the chip with the signals (ok, it does theoretically, but that amount is negliable with the dynamic losses in the gates mentioned below).

    You get power dissipation in each gate or buffer that changes state because of some signal, irregardless of the direction in which the information is flowing. You can not recycle this power. This comes directly from the basic principle behind CMOS technology (used by almost all digital chips today) - you are charging and discharging a capacitor.

    Typical example, that running signals in a circuit does not save power: take a ring oscillator (a number of negators wired in a loop). This circuit will oscillate (send changing signals through its loop) and consume an considerable amount of power.

    • Re:I call BS (Score:4, Informative)

      by jelle (14827) on Monday May 08 2006, @06:54PM (#15289291) Homepage
      Better link here

      http://www.eetimes.com/news/latest/showArticle.jht ml?articleID=187200783 [eetimes.com]

      Looks interesting. I wonder what they mean with 'taps', and if they calculated their power savings right (would each register need its own tap, or if not, is the buffer needed to boost the power from the loop included in the clock system power?)

    • Re:I call BS (Score:5, Informative)

      by CTho9305 (264265) on Monday May 08 2006, @07:00PM (#15289317) Homepage
      You get power dissipation in each gate or buffer that changes state because of some signal, irregardless of the direction in which the information is flowing. You can not recycle this power. This comes directly from the basic principle behind CMOS technology (used by almost all digital chips today) - you are charging and discharging a capacitor.

      You're half right. You're right that what's going on is a charging and discharging of a cap, but you're wrong that the charge can't be recycled. A conventional clock works by connecting the gates of a bunch of devices (i.e. capacitance) to Vdd, then after a little time connecting it to ground instead. Wait a little bit, then repeat. What effectively happens is that you dump some amount of charge from Vdd to ground each switch, and it's gone (i.e. it's heat now). A water analogy would be a tub of water above you (Vdd), a bucket in your hand (the capacitance), and the ground (gnd). You pour some water from the tub into your bucket (charge the cap), then dump it on the ground.

      It doesn't have to be this way. There are actually ways to charge a capacitor, and then pull the charge back out again (without dumping it to ground)! I'm going to assume you're familiar with LRC circuts, and how they can resonant when an impulse is applied. What's going on during the oscilattions? Charge is moving into the capacitor, and then being pulled back out to the inductor. The same charge goes back and forth, ideally forever (of course, in practice, the resistance isn't 0 so you put out some heat and the oscillations dies down). I'm not sure what exactly the water analogy would be - maybe a wave sloshing back and forth in a trough.

      I recently attended a seminar where the presenter talked about clocking based on LRC oscillations and he had actually fabbed chips that worked. The basic idea was to put an inductor on the die, and set up oscillations between the inductor and the clock load capacitance, which results in a ticking clock. Of course, you get a sinusoidal clock instead of a nice almost-square-wave, so your circuits have to be designed a little bit differently, but the point is, it works and is doable.

      Now, the technology described in this article, as best as I can tell, uses another idea - transmission lines. In a normal design, your clock grid basically looks like a bunch of capacitors with resistors in between (i.e. distributed RC). It takes time for a signal to propagate - signals propagate much slower than the speed of light, becuase you actually have to charge up the capacitance along the line through the resistance of the line itself. Imagine a long trough that's empty. You start pouring water in, and although water reaches the far side pretty quickly, you don't actually observe it until the water level at the far end is half way up. Signals propagate differently when wires are set up as transmission lines - they propagate at much closer to the speed of light, because you're actually sending a wave down the line (imagine creating a ripple on a trough of water, instead of actually filling and emptying the trough).

      Now, I don't understand how they combined charge recycling and transmission lines, I don't understand transmission lines all that well, but your arguments aren't good reasons to disregard the claims made by the company.

      If you're interested, here [cmu.edu] is a little bit of info about the talk I went to.

      Typical example, that running signals in a circuit does not save power: take a ring oscillator (a number of negators wired in a loop). This circuit will oscillate (send changing signals through its loop) and consume an considerable amount of power.
      If you created an oscillator between an inductor and a capacitor, on the other hand, once you started it going, it would continue for a long time with minimal energy injected in the future.
        • Last time I checked, speed of electron flow is only based on the material around it. Higher dialectric constant = lower speed of propgaition. Transmission lines aren't voodoo science, they are a property of the electrical length of the line and the rate of change of the signal on that line. It does not change the rate of propagation at all. Whether a given wire is 1" long, or 200 miles long, it will not change the speed of propagation.

          I didn't say electron flow speed changes. I said signal propagtion speed
      • I agree - it's probably real - more for the custom/semi-custom world though - people who can design datapaths with flow that physically follows the clock probably do well

  • Voltage flowing in loops.. (Score:3, Insightful)

    by t35t0r (751958) on Monday May 08 2006, @06:29PM (#15289177)
    What a breakthrough [wikipedia.org]
  • I think I can decrease my gas consumption by up to 75% by throwing square wheels on my car! Of course the reason would be because i would be 75% less likely to use a car that really cant go anywhere.
  • Since clocks take up a large percentage of the power and space on the chips, why not do away with them? Why not use a clockless CPU so results are available as soon as they are ready? There are some processors out there (ARM Amulet for instance) that do this, does it just not scale well to the high speeds we are used to now on our desks and laps, or is it just that current clocking cpu design is way ahead in terms of development?
    • Clocks are not a high percentage of the power. They're not trivial but mostly the problems with clocks is the length of the line. The bus between the register file and ALU is probably 1/20th that of the clock traces.

      Compared to all the other logic in a cpu from the decoders to the schedulers to the ALUs, load-store, and then all the support pipeline registers, control logic, etc not to mention the cache...

      The problem with "doing away with the clock" is being able to co-ordinate things in some usable amoun
    • agreed... especially when I read parts of TFA like this:

      " Multigig, have performed simulations that so far back up the company's claims, though the team is just about to start tests using actual chips, he said. "

      Given lots of unknown factors that can arise when you're using real electrons on real silicon, I like the idea, but I'll happily wait for the prototype before thinking this would be a net good thing.

      /P

    • Re:nah (Score:4, Interesting)

      by iamlucky13 (795185) on Monday May 08 2006, @06:09PM (#15289092)
      I share your doubts, but must point out that current hybrid cars already use regenerative [toyota.com] braking [honda.com]. The efficiency is only something like 30% (losses to transmit through the CVT, generate, store, spin the motor again), but it's still a little bit of return. Since the motor is already designed to act as a generator, it should be little extra investment to program the transmission to load the motor before mechanically engaging the brakes.
      • Is it really that inefficient? The electric motors used in the prius (for example) are reputed to be 85% efficient when acting as a generator, and something like 90% efficient when acting as a motor. Where's the rest of the loss, the charging system?
        • As the GP mentioned, CVT transmissions [wikipedia.org] (and other parts of the drivetrain) typically have other efficiency losses. (as a quick example... the reason that manual transmissions get higher MPG than automatics is that the torque converter in an auto has high efficiency losses)
        • Actually, it surprised me, too. I believe the major inefficiency comes from the battery. The number I gave was rounded off from the wikipedia entry (I hate turning to an unaccredited site everytime I need an answer, but it's soooo easy). I will assume the efficiency values you referred don't account for the CVT, which also run 80-90% efficient (compared to 90-95% for geared transmissions). So on these assumptions:

          eta(trans) * eta(gen) * eta(charge) * eta(discharge) * eta(motor) * eta(trans) =
          0.85 * 0.
          • Yes, batteries are the main loss. Also - their charging rate is the main limit on how much power you can recycle from braking.

            There's a new lithium ion variant with a nanotube-array electrode that might be a good solution for that. Charges 85% of capacity in minutes, which implies enormous power densities and minimal precentage losses to heat.

            (There's also a new lead-acid cell design using graphite rather than lead for the structural support of the plates that makes a similar sort of improvement in lead-a

    • Re:Radical Breakthrough? (Score:5, Insightful)

      by Mindwarp (15738) on Monday May 08 2006, @05:47PM (#15288978) Homepage Journal
      Why not? If this works it sounds like Moore's law would continue, and would give whatever company that deployed it first a performance advantage.

      Because first they're going to get a bunch of their theoreticians to work the math on the problem to make sure it's viable. Then they're going to get a bunch of their VLSI modellers to run virtual simulations on the clock modification to refine exactly how great the potential efficiency gain would be. If that turns out OK then they'd produce some simple mock-ups of the new clock architecture to make sure that it functions correctly in hardware. Then they'd go about the expensive and time-consuming process of redesigning the current chip architectures to include the new style clock. Then they'd produce an initial fabrication of the chip to run through extensive hardware testing (and on the inevitable failure they'd hop two steps back and try again.) Once they were happy with the design they'd scale up to full production and roll it out.

      Everybody in the microprocessor design world remembers this [wikipedia.org] all too well.
      • Yeah, strangely everyone remembers the FDIV flaw but nobody seems to remember this: http://apple.slashdot.org/article.pl?sid=06/01/24/ 1537231 [slashdot.org]

        Pentium 4 has 64 flaws, Core Duo has 34 and counting...

        At this point releasing a CPU with only one obscure FDIV bug would probably be a day to celebrate. ;)
        • FDIV wasn't particularly obscure; IIRC it went unnoticed for a very long time and affected many real world calculations. It was unlike many other errata in the regard that it was a documented function misbehaving and was not caught early. You could see it in action simply by loading up a spreadsheet app and doing a division. The software workaround wasn't that difficult, but the lack at the time of microcode support made it a big hassle.

          The Pentium also had the more egregious F00F bug, the nonexistent opcod
        • And then they'll find out that the patent for it is so tightly secured that noone can use it...

          Nah, that's when they bring in the bunny-suited lawyers to prove that they were the ones that invented the technology all along.

          :-)
    • "Intel is not going to redesign the Pentium tomorrow because of it," he said.

      Why not?

      For starters the automated design tools will need a rehack.

      Current synchronous chips use a "clock tree" to try to get all the flops and latches to clock at once. Then the design tools assume that the outputs flip at the same time and try to route the signals so they all get through the logic to set up the flops in time for the next clock.

      This scheme will produce waves of clocking that propagate across/around the chip. So

    • Re:Not so fast (Score:2, Funny)

      by Anonymous Coward
      Why? Quite a few guys got car battery adapted to work with laptops. Up to a week on a single charge! :)
    • So, would it be possible to make a 3-D chip?

      Yes, by stacking multipul dies in one chip. The problem however is thermal. It's hard enough getting one die to cool down. How do you propose flushing the heat of the dies sandwhiched in the middle?
    • The pathways that electrons flow through are pretty 'crazy ass' already. In fact, modern chips are already 'multi-layer' and so are already 3D. One of the biggest problems with stacking processing layers on a chip is that of heat removal. Each time you add an extra layer to the sandwich you make it a little harder to extract the heat from those internal layers.

      There have been some interesting research projects carried out using Sierpinski cubes as the chip fabrication layout, and using the channels in t
    • This was modded interesting?

      There's a circuit in the chip, which is not just "one line or branches"... it really already is a "crazy ass network" it flows through. You might be able to change the layout slightly and make the circuit itself more efficient by giving yourself the freedom of working in 3 dimensions... however I bet that would be harder to design, manufacture, and cool.

    • Re:Chip technology is awesome (Score:5, Informative)

      by slew (2918) on Monday May 08 2006, @06:19PM (#15289134)
      Ok nerds, tell me if this is feasible....

      P.S. In this context, the correct spelling of nerd is E-N-G-I-N-E-E-R ;^)

      So, would it be possible to make a 3-D chip? Where, instead of one line or branches that the electron follows but a crazy ass network for it to flow through?

      In most respects, chips today are ALREADY 3d in that there are multiple layers of planar (flat layers) metal wiring (anywhere from 4 to 8) connected by vias (vertical interconnect) over a single layer transistors. The routing of signals on each layer is on purpose designed to be a crazy-ass network (to avoid electromagnetic signal coupling noise between adjacent wires).

      However, in current technology, there's still only 1 layer of transistors, and the main limitation of adding more is that there's no good way to get rid of the heat of transistors. Even today, there isn't a good way to get rid of the heat of the transistors in the 1 layer of current chips, let alone a big pancake stack (or lasagna) of transistors. People are already starting to stack memory chips that don't get too hot together, and I'm sure they'll eventually start doing different kind of stacks too as they get better at figuring out the heat problem...

    • There's nothing inherently stopping you from making a fully 3d chip (existing chips already have many layers) however it's really difficult to get the heat out.

      Current CPUs keep the transistors very very close to the heatsink and still struggle to keep them cool. If you had a cube shaped chip then it would be near impossible (with traditional processes).

      There are some interesting projects to get miniture coolant pipes running through the chip, but that's a way off.
    • You're a bit confused, I think. If something is patented, then (in theory, at least), there is a publicly available patent disclosure that describes the technique in sufficient detail that anyone "skilled in the art" of its field should be able to read and implement it. Patents and trade secrets are mutually exclusive.

    • Re:Technical paper? (Score:4, Informative)

      by kent.dickey (685796) on Tuesday May 09 2006, @12:26AM (#15290942)
      The press has a knack for distorting stories and making it very hard to figure out real technical details.

      http://multigig.com/pub.html [multigig.com] has some whitepapers. I read the ISSCC 2006 slide set, which let me know the general technique.

      Basically, they produce a clock ring to produce a "differential" clock pair that after one lap swaps neg and pos and so it's frequency is tuned by it's own capacitance and inductance. They call it a "moebius" loop since it's not really a differential pair, but the clock wave makes two round trips before getting back to the start.. Neighboring loops can be tuned together (although if that's by just routing the wave throughout the chip I'm not sure). They didn't seem to mention synchronizing the period to outside sources, and I'm not sure how they'll be able to do that.

      The clocking is not the interesting part to me, but rather their logic strategy. The trick is that logic itself has no connection to power or ground. The clock nets provides the "power and ground" and all logic must be done as differential (a and abar as inputs, q and qbar as outputs). This is where they get the power savings from--the swings are reduced and there's no path to power or ground to drain away charge. Without really discussing it, charge seems to just shift around on internal nodes between the differential logic states. They then use pure NMOS fets for logic, which removes all PMOS. The logic will never read the power rail, though--it will always be a Vt drop. I just looked this over quickly, but it seems the full-swing clocks and lack of PMOS make this work out fine.

      For quick adoption, they'll need to work out clever techniques to connect this logic to standard clocked logic. Otherwise, it looks only a little bit easier to use than asynchronous logic. The issues they face seem very similar to asynchronous logic issues--tool support, interface to standard clocked logic, debug, test, etc.

      It's not vapor.

All trademarks and copyrights on this page are owned by their respective owners. Comments are owned by the Poster. The Rest © 1997-2009 Geeknet, Inc.