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Record Setting Silicon Resonator Reaches 4.51 GHz

Posted by Soulskill on Sun Mar 30, 2008 09:17 AM
from the faster-equals-better dept.
Technology Hardware
bibekpaudel brings news that researchers from Cornell University have developed a very small silicon microresonator that vibrates at the highest frequency ever recorded for such a device: 4.51 GHz. Typical quartz-crystal oscillators, commonly used in electronics as clock signals, are about a millimeter wide and operate in the KHz - MHz range. The newly developed microresonator measures 8.5 micrometers long and 40 micrometers wide, making it ideal for use in smaller circuits and microprocessing. Quoting: "One of the advantages of silicon microresonators is that they can be integrated directly into microchips using conventional manufacturing techniques, making them cheaper to produce and easier to fabricate small. Also, multiple resonators of different frequencies could be put on the same chip, says Ville Kaajakari, an assistant professor of electrical engineering at Louisiana Tech University. In a cell phone, for example, high-frequency resonators could filter out interference from other sources of radio signals."
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Submission: A Record-Setting Silicon Resonator at 4.5 GHz by bibekpaudel (1113383)
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  • Or at least it would have been if I had one of those.

  • this will benefit lower freq apps too (Score:5, Insightful)

    by v1 (525388) on Sunday March 30 2008, @09:53AM (#22911792) Homepage Journal
    Something I'm surprised the article did not point out is its applications in lower frequency use. If you want to create a stable clock that counts seconds, you don't make an oscillator at 1hz (one beat per second), you create one that does much more, say 1000hz, and then divide that by 1000. So if you are off by a few cycles it doesn't matter much. The greater this multiplication the better. So a fairly stable 4.5ghz reference could be divided down to make an extremely accurate and stable say, 500mhz signal.

    • Re: (Score:3, Insightful)

      by Gibbs-Duhem (1058152)

      The only thing that matters is the accuracy. If your 4.5gHz clock is accurate to 1ppm, it will be off by 4500 counts every second, which happens to be equal to a drift of 1 millionth of a second every second. If your 1Hz clock is accurate to 1ppm, surprise, it will also drift by 1 millionth of a second every second.

      Not to say you would use a 1Hz clock for a second counter, but this is more because it's convenient to not have to wait around in software for a clock edge to start calculations, and because th

      • A chip will generally have a constant drift. Say your 1Hz clock has a drift, you can fix the drift but previously you might have been a little more than a second after fixing it you were a little less than a second because the second actually landed down in the mid-point between the 1Hz. Its a problem of repeatable halfing the distance to the error, sure you'll never technically get there but at 4.5Ghz you can get much much closer.
        • That isn't how the process works. First, you can measure phase error (timing error) or frequency error of an oscillator continuously. So it needn't be a discrete-in-time measurement, and you can certainly measure errors of much less than one second on a 1 Hz signal. And your corrections certainly do not need to be discrete-in-time updates or, more importantly, corrections needn't come in multiples of 1 second.

          Updating physical clocks or correcting for their drift doesn't have to happen like leap seconds
    • Something I'm surprised the article did not point out is its applications in lower frequency use. If you want to create a stable clock that counts seconds, you don't make an oscillator at 1hz (one beat per second), you create one that does much more, say 1000hz, and then divide that by 1000. So if you are off by a few cycles it doesn't matter much. The greater this multiplication the better. So a fairly stable 4.5ghz reference could be divided down to make an extremely accurate and stable say, 500mhz signal
    • I would think you would calibrate the clock before you start dividing -- measure how many ticks you get in ten seconds, divide that number by 10, and divide your clock's output by that. Might be 998 on this one, 1003 on the next one.

      Still would be better the higher your starting frequency is, of course, since even if you calibrate perfectly, you still might be off by 0.5 ticks, but that 0.5 ticks represent less and less of an error the more input ticks you're counting per output tick.
    • I thought accuracy and stability of resonators depended on properly using the phase discriminators to align the resonators to within a 0.5% frequency variance of the warp core. Did I miss something?
      • That stage is where you are trying to make the end cycle as accurate as possible. If you can say, get a resonator to slip one or two cycles per a given period, it's to your advantage to go for a higher clock rate, and then divide down. When you divide down, you also divide down the error. So if your resonator might slip +/- 4 cycles in a period, and you are dividing it down by 8, then resulting signal may slip +/- 0.5 cycles per the same period.

    • The main advantage here is self-clocking chips with high frequency requirements. Typical low-frequency chips either can live with an external oscillator, are clocked by another control chip or aren't very frequency-dependent and use internal ring-oscillators.
      • I don't think it would be diving by N on every cycle, but adding 1 to a counter, and when the counter equals N, you do one of the low-frequency cycle.
        • Checking if a counter == x, for ever increasingly larger values of x, will still cause increased overheard. Storing the numerical value of 4.5 billion, in binary, is 100001100001110001000110100000000 unsigned. So a 32bit register won't even hold it, if my evaluation is correct.

          Whether or not the increased overhead is more detrimental than the increased accuracy is dependent on the application I suppose. But I guess all I meant to say is that 'more is better' is not always the case.
          • I'd imagine that this would not be something implemented in software but rather a dedicated system clock. The oscillator would be slaved to a tiny bit of dedicated circuitry that handles the count and all the outside system sees is the output number. It's a black box. From the point of view of the rest of the system, this would have no more overhead than a dedicated clock running at the lower frequency.

          • Re:this will benefit lower freq apps too (Score:4, Informative)

            by AdamHaun (43173) on Sunday March 30 2008, @10:46AM (#22912232)
            You don't do it with a CPU. You do it in hardware with a digital counter, like this:

            http://www.play-hookey.com/digital/ripple_counter.html [play-hookey.com]

            Dividing by two is easy -- just take the output of one of the flip-flops. Dividing by other numbers can be done by connecting the flip-flop outputs and/or their complements to an AND gate. This requires some extra circuitry and wiring, but in an integrated circuit the overhead will be insignificant. Even in a discrete circuit, if you make the reference 2^32Hz (~4.2GHz), you're only looking at maybe two counter ICs to divide down to 1Hz, although no counter IC I know of can handle a 4GHz signal.

            The real issue with using this would be whether your manufacturing process can make transistors fast enough for it. The quote in the summary suggests this will be popular in an analog role for high-frequency applications like wireless. Maybe we'll see discrete timing references too.

              • Yeah, I know Intel's CPUs can do it, but your average ASIC process is probably a different story...

          • Huh? You're checking a single counter to see if it overflows, nothing too taxing about that. The effort comes when the overflow happens, but it's really not much more effort
            Here's the logic:
            [0) Clear all counterincremented flags]
            1) Increment counter(1) by 1 (mod some number like 256, 65536, etc)
            2) if counter(1) = 0, it must have overflowed, so increment counter(2) by 1 (and set counterincremented(1) flag)
            3) if counter(2) = 0, it must have overflowed, so increment counter(3) by 1 (and set counterincremented(
            • Damn proofreading...

              3a) if counter(step) > 0, decrement counter(step) by 1
              should be

              3a) if counter(step) > 0, decrement step by 1

          • Re:this will benefit lower freq apps too (Score:4, Insightful)

            by Original Replica (908688) on Sunday March 30 2008, @11:48AM (#22912832) Journal
            Why is it necessary to count to 4.5 billion for a 500mhz clock? Every nine ticks of the 4.5ghz clock give one click to the 500mhz clock. Counting to nine is easy.
          • Its all done i hardware. There are no such problems.
      • Clock dividers don't work by dividing numbers. You have a counter, and each time the clock changes the counter increases. If you wanted to divide a clock by, say, 8, you would use a simple 3 bit counter, which would only require 3 flip-flops and would cause absolutely no performance hit and a tiny amount of die space.

        In-clock:0, Counter:000, Out-clock:0
        In-clock:1, Counter:100, Out-clock:0
        In-clock:0, Counter:010, Out-clock:0
        In-clock:1, Counter:110, Out-clock:0
        In-clock:0, Counter:001, Out-clock:1
        In-clock:1

  • I really hope these guys make it as integrated MCU modules soon. I can't claim that I've ever designed *really* small stuff, but I have some experience designing rather compact sensors,etc: the external crystal that drives the (I'm talking something between 20 and 200Mhz) MCU/DSP in these settings is typically almost as big as chip itself! It gets worse since typically you have to add discrete caps specifically for the xtal type/frequency and the whole thing makes your pretty, tiny, elegant, simple circuit

  • Neat (Score:4, Interesting)

    by tsa (15680) on Sunday March 30 2008, @10:15AM (#22911964) Homepage
    That is a fine piece of microengineering they show there! I'm impressed. I have one question, however: in the article it says: The Q factor for the Cornell device at 4.51 gigahertz is close to 10,000, which compares well with quartz resonators. Does that mean that although the frequency at which the device vibrates is higher than quarts, the accuracy is about the same?
    • I believe you are correct. Which basically means that for any given frequency compared to what you would have from quartz you will get a finer, more statistically predictable waveform.
    • No. While the frequency published is "clean", it's vulnerable to manufacturing skew, thermal drift, and other issues that will create skew in the clock. Quartz is useful because it's thermally and mechanically stable, due to being a crystal with a low thermal expansion coefficient and mechanically easy to machine within quite small tolerances.

    • Re: (Score:2, Informative)

      by cats-paw (34890)
      The Q is an indicator of the short term accuracy of the resonator. The long term accuracy is usually discussed in terms of temperature drift. The absolute accuracy has to do with how accurately you can produce a resonator of the desired frequency.

      The short term accuracy is referred to, by digital designers, as jitter and is a very important figure of merit in both digital designs and communication systems.

      The Q of this resonator is quite good, athough it's not unusual for quartz crystals to havo a Q of 50
    • If you used a frequency divider chain to bring the frequency down to the same as that of a quartz resonator, or if you expressed the noise from the oscillator in terms of a jitter then yes. However, the phase noise of an oscillator goes up by 3dB for each doubling of frequency, and there is a well known relationship between the Q-factor and the phase noise and a doubling of the Q-factor gives you 6dB of improvement in your phase noise. However, without knowing more its not easy to convert from the Q-factor
      • However, the phase noise of an oscillator goes up by 3dB for each doubling of frequency

        6 dB (or 20*log(N)).

    • Re: (Score:2, Informative)

      by EEmarty (795427)
      That is exactly correct. The Q of a resonator http://en.wikipedia.org/wiki/Q-factor#Electrical_systems/ [wikipedia.org] or oscillator determines it's efficiency at turning electrical energy into a usable oscillation. The real significance of this new resonator is that it can be incorporated into the same piece of silicon that the electronic circuit is built on. Currently if a circuit needs a high quality clock or RF signal it uses an off chip crystal oscillator to generate a reference clock usually at 10s to 100s of MH
    • i saw the post above about a Q of 10,000. Thats pretty high for the freq's involved. Q= 3dB bandwidth/frequency for resonators. But for HF, its very low. When they made HF (ie 1Mhz to 30Mhz) crystals for filters in the US, Q's were 100,000 or so. The crystals you get now days are so bad that you are lucky to find one out of 20 that has a Q of 50,000. There were special crystals used in certain applications with Q's of a million, but they are no longer made. What makes crystal Q so important is that
  • Traditional quartz [wikipedia.org] crystals are also made of silicon (SiO2). Silicon is the most abundant element in the Earth's crust, quartz the most abundant mineral. It's a lot cheaper than these new nanofabricated resonators, though the new ones are also made of silicon.

    • Re: (Score:2, Redundant)

      by norton_I (64015)
      No, quartz is silicon dioxide.
      • Er, silicon dioxide is made of silicon (and oxygen): "Si02" is "silicon dioxide", as I said. So is this new "silicon resonator" (and everything else made of "silicon chips").
    • CMOS is silicon-dioxide as well......or at least the substrate is.

      The point here is that instead of a discrete chip using a different fabrication process, a resonator can be built on a standard CMOS process. The article is very short on details of how this thing actually works but I was under the impression that we had such a technology already. It's called a ring oscillator....

  • And it's mechanical (Score:5, Interesting)

    by Animats (122034) on Sunday March 30 2008, @10:26AM (#22912066) Homepage

    Mechanical vibrations at 4.5GHz. Just think about that for a moment. A tiny piece of silicon, like a little tuning fork, wiggling back and forth 4,500,000,000 times every second. Without breaking or wearing out. It's not just electrons moving; this is a solid piece of material vibrating.

    • Re:And it's mechanical (Score:5, Interesting)

      by Jeff DeMaagd (2015) on Sunday March 30 2008, @11:14AM (#22912502) Homepage Journal
      Some of the macroscopic things that we understand almost intuitively don't hold very well in the micro world. For example, DLP projection uses mirrors that twist on a sliver of aluminum hundreds of times a second, but they're reliable for many billions of actuations.

      • That's true. I was once talking to one of the first designers of ink-jet printers at HP, and he mentioned that intuition about fluid behavior totally fails at that scale. They had to do simulations that modeled the interatomic forces to make inkjets work well.

    • All matter vibrates, and usually at a much higher frequency. It's called temperature. The reason larger structures break, is because they often contain tiny flaws in their structure (crystal lattice) that get bigger with each bend. The smaller the structure, the less probable there is a flaw. And the silicon wafers are a single crystal to begin with.

      I's be more worried about frequency drift because of thermal fluctuations.

  • Also, multiple resonators of different frequencies could be put on the same chip...

    Could this lead to improved performance for CPU/GPUs? My understanding is that there are parts of a chip that cannot keep up with the rest of it and the slowest part ends up being the one that sets the clock speed. Let's say some part(s) of the chip can handle being clocked at 4.5 GHz. But, other parts could only handle 3.0 GHz.

    Instead of clocking the whole chip at 3.0 GHz, one could put multiple resonators on the chi

    • Clocking different parts of a chip with separate completely independent clocks is a bad idea, because then different parts of the chip are in different clock domains. This causes metastability problems when the drifting clocks periodically align to violate the timing constraints of the other side of the circuit. Then you need synchronizing circuits, which add delays and don't guarantee anything (the more you wait, the more you reduce your chance of failure, but there is always a chance).

      • Clocking different parts of a chip with separate completely independent clocks is a bad idea, because then different parts of the chip are in different clock domains. This causes metastability problems when the drifting clocks periodically align to violate the timing constraints of the other side of the circuit. Then you need synchronizing circuits, which add delays and don't guarantee anything (the more you wait, the more you reduce your chance of failure, but there is always a chance).

        Thanks for the ex

        • But I'm having trouble reconciling this with how, for example, a GPU doesn't run (generally) at the same clock as the CPU, and yet they (seem to) get along just fine.

          That's because the CPU and GPU are not as tightly coupled, you have at the very least a PCI/PCI-E/AGP bus between them.

          To do the same inside a single chip, you need to define a communications interface between the separate modules. It is really a cost/benefit thing, you will gain performance by having some parts of the chip running at a higher
    • This is already done. Very few microchips nowadays only operate using one clock. Internally, the main clock (or in some cases multiple main clocks) are gated or divided down to drive lower-frequency components (albeit multi-cycle paths are used more often). The case you mentioned of a critical path running too slow can be alleviated by using multi-cycle paths.

      The problem, however, is that the rest of the chip still has to wait for the results from that critical path. Whether it's clocked slower, or allo
  • This article inspired me to dig out my ham radio crystals from the 1960's.

    "Rock-Bound" ham radio transmitters could only send messages at one frequency, so amateur operators sometimes modified the crystals to change frequencies. You'd tune the quartz crystals by grinding them with fine powder -- a few swipes would change frequency from 7130 to 7133 KHz (called "KiloCycles" back in the dark ages of the 1960's).

    I just photographed a couple such crystals and put them at http://picasaweb.google.com/BoomingHand [google.com]
  • "In a cell phone, for example, high-frequency resonators could filter out interference from other sources of radio signals." I'd be willing to bet this would have a benificial impact on battery performance. Small or large, I don't know.
  • 1. What is the temp coefficient for these devices? If it high, they will be essentially useless for communication usage, esp wireless and microwave.

    2. If they ever get into mass production, what is the projected cost per unit?

    I see these devices possibly used as clocks for computers, but why buy something exotic like this when you can just use a PLL that costs $0.50 ?
    • I forgot one other important parameter- Q. if the Q of the resonator is low, they will be useless in filter applications. Sometimes oscillators won't even start if the crystal Q is too low.
    • Another question is how bad the spurs (secondary resonances) are. This is important for filters; for oscillators you generally don't care.

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