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Intrinsity Claims 2.2 Ghz Chip 308

PowerMacDaddy writes "Over at SiliconValley.com there's an article about an Ausin, TX startup named Intrinsity that has unveiled a new chip that utilizes a new logic process with conventional fab processes to acheive a 2.2GHz clock rate. The company is headed by former Texas Instruments and Apple Computer microprocessor developer Paul Nixon. The real question is, is this all FUD, will the real-world performance be part of The Megahertz Myth, or is this thing for real?"
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Intrinsity Claims 2.2 Ghz Chip

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  • MHz (Score:5, Informative)

    by room101 ( 236520 ) on Tuesday August 14, 2001 @06:37PM (#2127850) Homepage
    The real question is, is this all FUD, will the real-world performance be part of The Megahertz Myth, or is this thing for real?"

    It doesn't matter if it is real or vapour, it will still fall prey to the "Megahertz Myth". Maybe someday, people will understand: non-similar architectures can't be compared by MHz alone. And even most similar arch's can't be compared via MHz, as the Intel v. AMD war will tell you.

    It is even worse than that! no single metric will ever give you the whole story.
  • by alannon ( 54117 ) on Wednesday August 15, 2001 @06:10AM (#2138496)
    I hate to add to an obviously silly conversation, but you state that Be could not run BeOS on the new G3 Macs because Apple would not release the specs for the new hardware.

    Good theory. And it is what Be said.

    Do you know how long it took for the PPC Linux developers to get the Linux kernel running on the new G3 machine? About 2 weeks. How many people work on the PPC specific parts of the Linux kernel? About 2 or 3. I can only guess how many software engineers worked at Be at the time, but I imagine more than 2 or 3. So, how stupid do you think people are? Be didn't get BeOS running on the G3 because -THEY DIDN'T WANT TO- just as Elwood said in a parent post to this. The fact that they lied and whined that it was Apple's fault made me lose a great deal of respect for them.

    I'd also like to point out that Apple is a HARDWARE VENDER. Do you think Apple makes money selling MacOS X for err, $89 or so? Of course not. It's a loss-leader to get people to buy their hardware which has a higher markup than most consumer PC hardware. People have been talking for years about how Apple should give up on hardware and moving to software. It won't happen. Apple losing control over their hardware platform would greatly reduce the added value that their products give over consumer PCs.
  • by c-w-k ( 142705 ) on Tuesday August 14, 2001 @06:43PM (#2140479)
    eetimes [eetimes.com]
  • by taniwha ( 70410 ) on Tuesday August 14, 2001 @07:05PM (#2151323) Homepage Journal
    From memory 8080s hade some dynamic nodes - the upside is that you can squeeze some extra gate delays out of some circuits (dynamic carry chains are a good example) - the down side is a chip with a MINIMUM clock speed - which makes test (scan and ATE etc) much harder - those expensive testers we test chips with just don't go that fast.

    Given that net delays are becoming the gating factor in big chip designs dynamic logic seems to me to just be a sideshow - unless the long wires are themselves the dynamic nodes (transmission lines with solitons moving on them?) now that would be interesting ...

    Potentially much more interesting IMHO is clockless asynchronous logic - but CAD tools just aren't up to supporting this methodology (oh yeah and the synchronous clock based mindset is pretty entrenched too).

  • Re:Just a guess... (Score:3, Informative)

    by b0r1s ( 170449 ) on Tuesday August 14, 2001 @06:47PM (#2156783) Homepage
    Looking at some of the people working for/with this company, I'm not gonna jump on the "it has to be a myth" bandwagon....


    Terry Gannon - Independent consultant. Terry founded TeraGen and has held executive positions at Xilinx, Seeq and Sun Microsystems.

    John Payne - Chairman of Fast Chip. John is the former president and COO of IDT; president and CEO of Star Semiconductor; president and COO of Rendition.

    Rick Shiner - Venture partner with Woodside Fund. Rick is the former president and CEO of Hotrail; president and CEO of Exponential Technology. He has also held executive positions at Apple, Intel, Motorola and Wang Laboratories.

    Tom Whiteside - Independent consultant. Tom is the former president of MIPS Technology. He also served as the Vice President of Microprocessor Development at IBM and most recently served on the board of Chicory Systems.

    Bill Goins - Marketing Angel. With over 25 years of marketing leadership, Bill founded Powered,Inc. and performed COO, VP or executive marketing roles at Micron Electronics, Power Computing, Apple, Dynamac and NL Information Systems.


    There really is some intelligence and talent working for this company, I'd like to see what they can produce. Maybe in a few months, if there's no decent benchmarks (by that time, someone somewhere should have written code to use their logic, right?), then I'll jump on the "it's a myth" bandwagon, but I'm willing to give them a chance first.
  • by Elwood P Dowd ( 16933 ) <judgmentalist@gmail.com> on Wednesday August 15, 2001 @01:28AM (#2164844) Journal
    You realize that's bullshit, right? Jobs and Gassee are both notoriously hard to deal with. Someone got rankled.

    Saying that their OS was running apps slower is kindof silly when it's not preemptively multitasked. If you really wanted to, you could just steal the processor from the OS and never give it back.

    And Apple stopped sharing specs because they didn't want harware competition.

    That said, Be didn't stop porting because they needed the specs. They didn't need the specs. They stopped porting because they wanted to stop. Perhaps because they wanted to know that Apple would support them in the future, but whatever.
  • by robbyjo ( 315601 ) on Tuesday August 14, 2001 @07:19PM (#2170187) Homepage

    It's not MHz that determines the speed. It's just one of them. The rest would be:

    • Pipeline or non pipeline with the number of stages. The more stages the better (but watch out with the cache trashing issue like in P4).
    • Scalar or vector
    • How many n in n-Multiscalar
    • RISC or CISC
    • Internal bus speed
    • Memory bandwidth
    • I/O speed

    And many more. If you have learnt Computer Architecture, then you'd certainly able to list hundreds more.

    Moreover, Apple wants to play catchup [theregister.co.uk] with x86... Hmmm... Do you smell something fishy?

  • by Christopher Thomas ( 11717 ) on Tuesday August 14, 2001 @07:23PM (#2170205)
    What is dynamic logic? How is it different from conventional logic wired together with different types of gates?

    Both dynamic and static logic use logic gates or blocks that are wired together. The difference is in how the gates are implemented internally, and how they pass data back and forth.

    CMOS is a good example of static logic. It uses pull-up and pull-down transistor networks to make sure that outputs are always strongly asserted. This makes CMOS gates big and makes input capacitance larger than it otherwise needs to be. But, it's well-understood, has a few attractive features, and has a whole slew of design tools built for it.

    Precharge logic is a good example of dynamic logic. It uses the parasitic capacitance of the output line to store the output value. The output node is charged up on one half of the clock (precharge phase), and left floating on the other half (readout phase). During the readout phase, the inputs are asserted. Inputs are fed into a pull-down transistor network that drives the output low if it should be low, and leaves it alone if it should be high. This style of logic takes up half the space of CMOS logic, has half the input capacitance, and has stronger driving capability (NFETs pulling down typically drive 2x-3x more strongly than PFETs pulling up). This means that if you play your cards right, you can make precharge logic circuits that are faster *and* more compact than CMOS logic circuits. The downsides are that designing and verifying precharge logic is a royal pain, and that you have to have a clock input into the logic block.

    The article describes a more complicated dynamic logic scheme with a four-phase clock. These kinds of schemes have been floating around in research literature for years, but are usually not used because of the greater complexity and fewer tools available.
  • by StandardDeviant ( 122674 ) on Tuesday August 14, 2001 @07:47PM (#2170292) Homepage Journal
    ... for a while in the late '99-early '00 region as a PFY sysadmin. If they say they can do something, I'd lay good money on them doing it. The level of expertise and knowledge displayed by their staff was stunning. More specifically, I do recall some of the engineers talking excitedly about this stuff at the time and mentioning breaking the 2GHz barrier (keep in mind this was in late '99), so this is hardly a publicity stunt as it's been in the works for quite a while if it's the same thing I was hearing about then...

    They were the Austin branch of a company called Exponential Tech. Doing a google on that should bring you up to speed on the Apple connection. I wouldn't really consider them a startup as they've been around for several years and have designed a number of very popular things (e.g. DSPs for other chip manufacturers).

    They were a great bunch to work for, especially for being kind to a rather wet-behind-the-ears sysadmin like I was. The only downside to working there was the gawd-awful commute I had to do from far NE Austin to far SW Austin. (If you're an EE type who'd like to live in Austin, they'd IMHO be a great place to work [intrinsity.com]for)

  • For embedded systems (Score:2, Informative)

    by trixillion ( 66374 ) on Tuesday August 14, 2001 @08:50PM (#2170470)
    A couple of notes:

    1) This is old news. You can find a much better story [eetimes.com] from yesterday over at the EETimes.
    2) This is for embedded systems and is not really relevent for PC based systems.
    3) This isn't even taped out yet... matter of fact they are not even planning to have the design done for another 18 months... it is vapour until you can actually buy it and that isn't slated until sometime in 2003.
    4) This might give Transmeta a serious run for its money if it is ever produced, because they are both in the same space... Of course, TMTA being still around in 2003 is a bit on the presumptious side.
    5) Oh never mind, why do I even bother...
  • by VAXman ( 96870 ) on Tuesday August 14, 2001 @09:32PM (#2170543)
    Intel uses it to sell it's Xeon chips to businesses at much lower clock rates and higher prices than the P4; Intel uses it to explain why Itanium runs at 800MHz; AMD's new chip runs at 1.5GHz, but they say it outperforms a 2GHz P4; Alphas run at 1GHz but are acknowledged to be much faster than a P4; Sparcs run at 900MHz, yet are also acknowledged to be better performers than a P4.

    There seems to be some confusion. SPARC, Athlon, Alpha, and Itanium are not faster performers than P4 (except the Itanium which beats P4 at FP).

    Let's have a look:

    P4/1.8GHz: SPECint - 574, SPECfp - 618
    Athlon/1.4GHz: SPECint - 495, SPECfp - 426
    Alpha/1001MHz: SPECint - 561, SPECfp - 585
    SPARC/900MHz: SPECint - 439, SPECfp - 439
    Itanium/800MH: SPECint - 314, SPECfp - 655

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