New Photolithography Process 81
dragons_flight writes "Motorola has announced a new photolithography process capable of making chip features smaller than 100 nm, with the aim of eventually going as low as 13 nm. For reference, the current next-generation standard is 157 nm."
Features != transistors.... (Score:4, Insightful)
Making small features is only a very small part of making a working chip.
Is there a semiconductor physicist in the house? (Score:1, Insightful)
Then, assuming that transistors scale down nicely by two orders of magnitude from the current state of the art, how much voltage do you need to bias them? Even on today's 1.8V ICs, you're looking at a gate-drain voltage of 0.6V -ish. Is this compatible with the requirement to reduce the operating voltage to avoid heat death?
Etching really small things into silicon... good work, but I think there are many major engineering challenges to overcome before they can say "we've got a 0.001 micron process, ner ner ner ner ner". I shudder to imagine how many times they're going to have to revise their SCMOS design rules between now and then.
Why do I get the feeling I'm spoiling this for everyone else?