64 Mbyte Write once CMOS Chip from Standard Fabs

brian wang writes "Matrix semiconductor has taped out 64 Mbyte write once chip. It is 8 layer memory that can be made at standard fabs. They will be made at Taiwan Semiconductor initially in a 0.25micron process. It will be compatible with Flash. Obviously when they move to 0.18 micron and 0.13 and 0.10 micron processes that already are producing chips the memory size will shoot up to rival CDRoms from single chips. Revolutionary impact for handhelds, PCs, ROMDrives etc..." See, I knew it: Little is better.

Re:OS BIOS

[toastyman]

Actually, no.

The tiny bit of ram that the BIOS uses to store all your settings between boots is made of CMOS. The BIOS itself is stored in regular PROMs or in more recent years flash rom.

So WHAT capacities are possible?

[Tsar]

"Using a 3-D fabrication method that deposits layers of circuits with a modified CMOS process, the technique can yield nine to 10 times the amount of chips per a given wafer, providing a cost advantage over traditional flash memory, according to Matrix..."

So we could see a CDROM-capacity write-once "consumable memory" chip that was the same size as a 64MB chip now. Nice, but the article later says:

"The company said it sees no limit to the number of layers that could be added to a device."

How does that jive with the earlier stated scalability of 9-10x?

"'If they can really do this and produce working devices, it is very hot,' said Richard Wawrzyniak, an analyst at Semico Research (Phoenix)."

Oh, so heat is the limiting factor! <g> Seriously, though, I agree with his assessment—having the devices actually work would greatly contribute to their coolness factor.

Misleading...

[Anonymous Coward]

The big news is not what's in the title. They've had large write-once memories before; they're called PROMs(Programmable read-only memories). The news is that they supposedly have a new 3-D fabrication technique.

Using a 3-D fabrication method that deposits layers of circuits with a modified CMOS process, the technique can yield nine to 10 times the amount of chips per a given wafer, providing a cost advantage over traditional flash memory, according to Matrix (Santa Clara, Calif.).

Perhaps in the future your processor will be the size and shape of a die or cube of cheese.

More info at their website

[Myco]

The article is a bit lacking on consumer-relevant details, but the marketese on their site [matrixsemi.com] gives you a better idea of that stuff.

Notables:

• Price: "Matrix 3DM cards will be comparable in cost to 35mm film and work in a similar fashion"
• Longevity: "Matrix 3-D Memory's array structure results in an archival storage device capable of storing data for more than 100 years."
• Scaling up: "By leveraging the same infrastructure as the rest of the industry, Matrix 3-D Memory will scale at least as fast as other semiconductor technologies, maintaining its significant cost advantage with future process generations."
• Compatibility: "Interchangeable with re-writeable flash cards"
• Capacity: "Comparable cost per megabyte to optical and magnetic storage"

Re:OS BIOS

[Anonymous Colin]

30 seconds... You could just store an image of the RAM of a booted Linux system and boot INSTANTLY...!!!

Hmm, I guess to you, POST only means a piece of wood stuck in the ground.

Restoring the system memory to a known state is NOT ENOUGH. The hardware has to be initialized to a known state as well. This can't be done by simply loading memory somewhere. Some devices require resetting (because they have write-only control registers and you can't know what state they are in by reading status), a sequence of commands/register writes with appropriate time delays and often a register needs to be programmed with several distinct commands, in the right order.

Simply having a RAM image just doesn't cut it, you need startup code as well. Also, the devices POSTs (Power-On Self Test) impose delays that the OS writer has no control over.

Colin

Re:More info at their website

[Anonymous Coward]

Scientific American has an article with an explanation of how Matrix did the 3D chips and what the future possibilities are

http://www.sciam.com/2002/0102issue/0102lee.html