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Technology Hardware

From Silicon To Microprocessors 174

prostoalex writes "Jim Turley from Embedded Systems Programming magazine answers the question of where microprocessors come from. While the public generally knows about the silicon and microprocessor vendors, few can describe the process of turning the beach sand into the latest and greatest several-hundred-dollars-worth CPU."
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From Silicon To Microprocessors

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  • One supplier (Score:5, Informative)

    by ackthpt ( 218170 ) * on Wednesday February 04, 2004 @07:14PM (#8184507) Homepage Journal
    When I lived in Midland, MI (home to Dow and Dow Corning) 'silicon' wasn't uncommon in casual conversations, particularly in a city of 40,000 with a large engineering population. Dow Corning, besides silicone compounds also provides silicon to a local company literally in the sticks, Hemlock Semiconductor [hscpoly.com]. Some nice stuff on their site regarding products, 1 [hscpoly.com], 2 [hscpoly.com]

    I'd always thought these materials were made in hot, dry climates, like Arizona, yet there was a supplier right in my backyard.

  • Clean Rooms (Score:5, Informative)

    by nil5 ( 538942 ) on Wednesday February 04, 2004 @07:15PM (#8184528) Homepage
    The only thing I don't like about the process is the working conditions: annoyingly loud!
    For those of you that have never been in a clean room, there is a tremendous amount of ambient sound due to the very important air cleaning/circulation system. In order to make the clean room "clean", there can only be so much dust particles in the air. (e.g. 1ppm) (there are actually different classes of clean rooms)

    The ramification of this is that one can hardly hear one's voice. Personally, I'm glad I'm not in the semiconductor field :)
  • Try Intel's museum (Score:5, Informative)

    by badzilla ( 50355 ) <ultrak3wlNO@SPAMgmail.com> on Wednesday February 04, 2004 @07:18PM (#8184560)
    If you can visit Santa Clara USA then Intel's museum [intel.com] has a nice introduction to the process of turning sand into chips.
  • by chullymonster ( 695441 ) on Wednesday February 04, 2004 @07:32PM (#8184713)
    Have a look at MEMC's website (www.memc.com), they produce silicon wafers like the ones in the article. The site has some nice pics and animations of their manufacturing process.
  • by Anonymous Coward on Wednesday February 04, 2004 @07:33PM (#8184717)
    Having smaller die sizes is not good just because you can put more dies on a wafer. It is because your yield will improve. Dust/contamination is the real enemey, and bigger dies have an (exponentially or even worse) higher risk of having one dust particle destroying the chip function. Cutting the size with 10% may well lower the production cost by 50%.

    And that is ofcourse why moving to a smaller technology (eg from .18 to .13) can be a real money saver (next to allowing higher clock rates).
  • Re:near-first post (Score:3, Informative)

    by Spudley ( 171066 ) on Wednesday February 04, 2004 @07:40PM (#8184776) Homepage Journal
    Technically, East Germany was 2nd World, until unification.

    The term "3rd World" was coined to describe the rest of the world, after NATO and the Warsaw Pact nations, which were implied to be the first and second worlds respectively.

    Although that definition didn't stick, the phrase did, and quickly came to take on the meaning that we all know, since most of the nations it included were desperately poor.

    (Here endeth the history lesson ;-) )
  • by stevesliva ( 648202 ) on Wednesday February 04, 2004 @07:52PM (#8184885) Journal
    I agree. Even given a perfect mask, you can still blow the chemistry (implants, trenches, diffusion, whatever) for a given process step pretty easily. It also doesn't seem to mention the chemical-mechanical polishing needed to smooth the wafers after certain steps-- that's easy to screw up also.

    But as far as an article targeted at a total layperson goes, it's okay. Not that most laypeople don't quickly lose interest when you start talking about wafers, masks, reticles, photoresist, process steps. You always have to start with the broader concepts and see when their eyes glaze over:

    What do you do?
    I work at a place that makes computer chips
    Oh really? What kinds?
    All kinds. I work in the ASICS group.
    ASICS? Like the sneakers?

  • by Anonymous Coward on Wednesday February 04, 2004 @07:54PM (#8184906)
    Easy, The octagonal intel chips was probably cut as a square. The corners were just wasted space. They were octagonal due to lithogrphy reasons, not to save space. Triangular chips are even worse then square in that regard. For the same area the crossection is larger making layout and lithography harder. Now triangles could still ork for small chips but if they are small you are not wasting much space anyway so its not practical to change your process to squease out an extra 1%.
  • by stevesliva ( 648202 ) on Wednesday February 04, 2004 @08:02PM (#8184981) Journal
    I guess focus could certainly be a problem, but as far as wafer sized masks go, if you're creating a mask that costs many thousands of dollars, you're far less likely to have a defect in the mask if the mask is only the size needed for one die, and not the entire wafer. And since certain masks are not 1:1 masks but 2:1 or 4:1 masks, you'd might need a 1200mm mask for 4x a 300mm wafer. A 1.2 meter mask. See a problem?
  • Projection blur (Score:3, Informative)

    by Atario ( 673917 ) on Wednesday February 04, 2004 @08:03PM (#8184987) Homepage
    I think he's talking about the fact that focus is consistent on a sphere, not a plane. Since the chips are flat, the image you project on them is only perfectly focused on a circle (the intersection of the perfect-focus sphere with the plane of the wafer). You can see this happen with regular slide-, TV-, or film-projection as well.

    It sounds like they focus the center exactly and let it get blurry the further out you go (this is the case where the plane is tangent to the sphere -- a zero-radius circle of focus, which is of course a point). I would think they would set the cicle to be larger in order to get more area of better focus, but maybe having some blurring in the center screws up their designs more.

    Dunno, IANAMCFA. (Dare anyone to figure out what that one meant.)
  • Too elementary... (Score:5, Informative)

    by sharkb8 ( 723587 ) on Wednesday February 04, 2004 @08:11PM (#8185059)
    They don't use beachsand, that's silicon dioxide (SiO2), also known as quartz.

    Pure silicon chunks are actually made from condensing a very pure Silicon gas called Silane. The chunks are broken up, and melted in a very hot furnace, with a crucible made out of quartz(usually). Any doping, or impurities to give the silicon it's different electrical properties are added at this point. Boron (B) is fairly common.

    Then, a nice perfect seed crystal of silicon is dipped into the molten silicon which starts to crystalize around the seed crystal. The growing crystal is turned and slowly pulled out of the liquid silicon as it grows to help keep it regular. The result is called a boule, or "the bologna looking thing"

    As a side note, the doping is usually too high at the top of the boule, and too low at the end of the boule, so only about the middle 25% is used.

    Then it gets sliced into wafers. etc. etc.
  • Mistakes? (Score:5, Informative)

    by Anonymous Coward on Wednesday February 04, 2004 @08:12PM (#8185066)
    There are more than a few nits...

    (1) Silicon is not sand. Sand is silicon dioxide (well, most sand). It needs to be reduced (the oxygen needs to be removed) and purified. And purified. And purified. (I believe Brazilian quartz is actually the preferred stock for silicon dioxide, rather than sand, due to its purity.)

    (2) Photo-resist does not need to be electrically conductive. It does need to be capable of resisting attack by whatever chemicals are next in the step (especially the HF). Since they're usually polymers that are either polymerized or depolymerized by the exposure, they generally are not conductive.

    (3) Current generation laser steppers are not EUV. (They are UV, maybe DUV, being slightly less than 1/2 the wavelength of visible indigo.)

    (4) One could get the impression that each chip on the wafer is processed separately at each step.

    (5) Fabs and foundries are related but distinct entities. (I personally have worked in a fab, but never a foundry.)

    (6) It's the mask that is imprinted on the wafer's photoresist, not the chip.

    (7) Moore's law is incorrectly repeated. This is especially bad because it claims to be correcting the common belief (which it probably is). Moore's law was about the economics of chip density -- the most _cost effective_ density doubles every 18 months.

    (8) I've usually heard and talked about individual die and multiple dice. (And breaking up wafers into chips is called dicing.) Maybe others call them (plural) die, but not everyone.

    (9) The 200mm wafer area calculations are wrong. A 200mm wafer has a radius of 10cm; the area is therefore (10)^2*pi ~= 310cm^2. So one won't get 986 die from a square wafer and only 279 from a round one.

    (10) Lots and lots of companies don't build their chips on the smallest feature sizes possible. Very few can afford to manufacture 90nm chips at this point, so the bulk of chip _designs_ are manufactured at .13u, .18u, or larger.

    There are probably many more errors...

    RJ

  • by stevesliva ( 648202 ) on Wednesday February 04, 2004 @08:15PM (#8185082) Journal
    In and around the fab, there's a huge range of skills necessary, from babysitting machines to trying to figure out quantum mechanics.

    To work in a bunny suit on the production floor? A high school diploma is often enough. To work in test/yield improvement? An EE degree, perhaps. To actually develop the bleeding edge processes? A PhD in physics.

    There's far more to it than that, of course. And the actual chip designers could be across the parking lot or around the world.

  • by Anonymous Coward on Wednesday February 04, 2004 @08:50PM (#8185400)
    You still need humans for a lot of the alignment-and-inspection work that the machines simply can't do themselves.


    Also, mostly the machines are made by different vendors, so they don't have communication protocols to "talk" to one another, or to talk to a central dispatching control system. Therefore you need operators to move parts from machine to machine, and to select the appropriate programs to run on each machine (the parts pass through each machine multiple times, getting different processing each time).


    Finally, the machines do break, and you want somebody there to intervene before several tens of thousands of dollars worth of parts get crushed.

  • by burnin1965 ( 535071 ) on Wednesday February 04, 2004 @09:15PM (#8185635) Homepage
    Unless you are talking about a clean room from the late 70s or the 80s, its more likely that the noise you are hearing is from the exhaust systems sucking fumes from processing equipment.

    The materials used to produce semiconductors are extremely deadly to humans as are many of the process by products.

    Pretty much every processing tool has multiple exhaust connections which remove potentially harmful fumes to a scrubbing system on the roof that removes the toxic chemicals which are then treated and disposed.

    There are other noises from the tools and support equipment but I assume you thought it was the laminar air flow filtering system because it sounded like high volume air movement. They do move high volumes of air but you don't want the air moving too fast as it will stir up any particles that may be present in the room.

    burnin

    oh, I do work in a clean room, have since 1989.
  • by coastwalker ( 307620 ) <acoastwalker@[ ]mail.com ['hot' in gap]> on Wednesday February 04, 2004 @09:38PM (#8185821) Homepage
    Square ( or rectangular) because the silicon crystal lattice wants to break along perpendicular directions and square because a diamond wheel doesnt change directions very easily. Any other shape would result in more broken chips and lower yield and higher prices.
  • Re:near-first post (Score:2, Informative)

    by flint ( 118836 ) on Wednesday February 04, 2004 @09:39PM (#8185830)
    You are correct sir.

    And, if it's history education we're after... Sauvy, a French demographer, is generally credited with the term. He wanted to convey how Third World countries are exploited by the first and second. It was an analogy dating to the French Revolution when the first two estates (clergy and nobility) exploited the third (the commoners).

  • by burnin1965 ( 535071 ) on Wednesday February 04, 2004 @09:39PM (#8185837) Homepage
    In a semiconductor factory yield is a measure of the percentage of good die versus the total number of potential die on a wafer. It is not the measure of the total number of die produced from a wafer and is therefore not directly affected by the size of the die.

    You are correct that smaller die sizes produce more die per wafer, however, shrinking the structures in a die's circuit make it more susceptible to failure due to contamination. Therefore you are actually wrong when you state that a smaller die will yield more.

    You can think about it this way. If you have two parallel conducting poly lines that are seperated by an insulator that is 1 inch wide and you drop a penny on the insulator it is likely that the insulator will still work because the penny, which is the contaminant, is not large enough to short across the insulator. If you take that insulator and shrink it down to 1/4 of an inch and drop the same contaminating penny on it there is a chance that it will short the two poly conductors across the insulator and destroy your circuit. Take that same circuit and shrink it to 0.01 inch lines and suddenly your process that ran wonderfully is destroying every die on the wafer because the penny is guaranteed to short the circuit every time.

    So what you can derive from this is two things. First, the smaller contaminating particles are the less likely they are to destroy a die and may actually be acceptable, the smaller a die gets the more likely it will be destroyed by smaller particles and you plunge into a never ending battle of cleaning up smaller and smaller sized particles.

    Speaking from experience I watched a process that ran for 10+ years and worked fine. Once the geometries in the die shrunk to .35 microns the same process was destroying die because the tiny particles it introduced suddenly were big enough to start creating a significant number of shorts. Needless to say I had my work cut out for me as the equipment required some reengineering along with the process.

    burnin
  • by burnin1965 ( 535071 ) on Wednesday February 04, 2004 @10:08PM (#8186047) Homepage
    I agree that humans are still needed for many inspections and troubleshooting, however, that's about where it ends.

    Manufacturers are able to completely automate the entire wafer handling process. The alignment for handling and processing is many times better than what any human could do.

    And there have been standard communication protocols for interconnecting tools and systems for many years now. The two most common protocols are SECS and GEM.

    burnin
  • Re:Mistakes? (Score:1, Informative)

    by Anonymous Coward on Wednesday February 04, 2004 @10:11PM (#8186061)
    A few more clarifications here: I am a yield enhancement engineer at a fab here in the US. First, the wafers are silicon, not silicon dioxide. Oxidation of Si is extremely important in the process, but it is not the starting matrial. You are correct that resist being conductive is totally unnecessary. Current generation steppers are not steppers at all, they are called scanners (they scan across the reticle in one direction while also stepping across the wafer. This has several advantages). Also, current generation is usually 193nm, which is beyond DUV, but not yet at EUV. This number refers to the wavelength of light used to expose the resist, not the feature size it can create. It is very common to use "die" for multiple chips. AFAIK, nobody has volume production of 90nm chips yet, but it is very close. I could go on for days, but I think this article gives people the impression that fabrication is pretty easy. Depending on the number of steps, the cycle time to produce and test a complete wafer can be anywhere from 30 to 90 days. Compare that to the time it takes to make things like a car, and you will begin to feel like you are getting a deal on your next cpu.
  • by lingqi ( 577227 ) on Wednesday February 04, 2004 @10:27PM (#8186226) Journal
    * when cutting the ingots, people almost ALWAYS use a ring-blade; where the blade is on the inner edge of a ring larger than the ingot, and ingot is sliced. extra points for anyone who know why.**

    * ingots are not always "grown." (think dipping candles) there is also a technique where you start off with a polychrystaline ingot and use localized heating to progressively monocrystalize it by localized melting. The technique is similar to one of the methods of removing impurities from iron bars.

    * CMP is damn cool. I mean, it's nice and all hearing about "polish to within an atom" precision, but if you take a polished wafer, it would make the best mirror you'd ever own. Granted silicon is not the perfect reflective surface, but you won't get a mirror more accuratly shows every feature on your face. =) Otoh, when dusts and stuff DO get into the CMP machines, though, it scratches the wafer. Though you don't see it, when you trace failures on the wafer the failing gates would generally follow an arc shape (corresponding to the wafer and polishing head rotation), and from that you get the CMP machine checked out.

    random junk I thought that was kinda neat.

    ** I used to know about 3 years ago but then I forgot. so don't expect like a correct answer or nothing.
  • heh (Score:1, Informative)

    by Anonymous Coward on Wednesday February 04, 2004 @10:27PM (#8186229)
    yea he completely skipped over the whole process of making semiconductor matirial. The silicon used it not pure silicon its doped to add impurities to change the molecular stucture of the matirial and produce the two differnt varieties of silicon semi conductor n type and p type

I tell them to turn to the study of mathematics, for it is only there that they might escape the lusts of the flesh. -- Thomas Mann, "The Magic Mountain"

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