The Arrival of Very Small Memory

Roland Piquepaille writes "After the ages of DRAM and SRAM memories, is this time for nanotech memories? ExtremeTech says that "molecular memories" as well as memories based on carbon nanotubes are emerging. With these nanotech memories, several startup companies are envisioning future chips mixing logic, memory and reconfigurable computing elements. One of these promising startups is ZettaCore, which has built a prototype of a molecular memory designed to replace both SRAM and DRAM kinds of memories. These molecules, which are about 1 nanometer in size, are also self-assembling, meaning that they can be manufactured with existing equipment used in the semiconductor industry. This overview contains more details about the technology and includes a diagram of these molecules in a memory array."

Already being done with conventional technology

[Space cowboy]

Xilinx [xilinx.com] have silicon with embedded PowerPC processors, BlockRam (chunks of pre-generated SRAM) and huge swathes of FPGA cells and interconnect. The chips have other abilities too - built-in 18-bit multipliers and communications channges (10 Gbps/channel, 20 channels!). All very cool stuff. Very expensive too :-(

I'm sort of surprised there aren't more FPGA-hackers than there appears to be. It's not hard to learn verilog (very similar to C), and despite what most FPGA designers will tell you, as long as you keep your mind focused on 'everything happens in parallel', a decent programmer can produce good FPGA code too. The start kits (300,000 gates, about enough for a hardware JPEG core and maybe a network MAC) are cheap (100 or so), and designing a processor [fpgacpu.org] is a pretty simple operation, and immensely gratifying :-)

Just my thoughts,

Simon

Re:Perfect for 64bit computing.

[millahtime]

"18Tb of RAM"

The problem I would see with this is the addressing of the ram. You couldn't use straight pins to do that high of number for addressing and what speeds would the buss work at. There are other limiting factors on how much ram you can really work with.

Re:Perfect for 64bit computing.

[silas_moeckel]

I beleive 4GB Dimms are as large as they can go do to limitations in the addressing lines (pins) at 32 (havent checked this might be wrong). So untill a new form factor is released thats what we are stuck with. I would differ on the max expandability most MB's I have seen are running 4 DIMM slots per proc. I beleive this is the max they were designed to handle on there embeded memory controler. I am speaking of the Opterons of course. The PIV's currently have chipsets supporting piles and piles of DIMM slots at least 16 last I saw possibly more (64GB is the current max and I think they did that with 2GB sticks). So with these numbers and 4GB dimms thats 32GB in a 2 way Opteron setup and 64GB on an intel. The nice thing is the 8 way Opterons would be running 128GB max though thats a massive motherboard to support that.

Overall I dnt see this tech realy reducing the size of the ram on pin count alone more it will reduce the power consumption and profile of the dimms what increasign the potential density of a new replacement for DIMM's.

Re:Perfect for 64bit computing.

[Anonymous Coward]

DDR supports 1Gb chips. They can be used to make 4GB DIMMs.

DDR-II makes possible to use 4Gb chips. They can be used to make 16GB DIMMs. However, it will take a few years before manufacturing technology improves enough to make manufacturing of 4Gb chips possible.

Re:Already being done with conventional technology

[Anonymous Coward]

The FPGA hackers are hanging out at OpenCores [opencores.org].

Re:NExt step

[carm$y$]

Johnny something

Mnemonic. Johnny Mnenonic. Tough word, isn't it? :)
And it wasn't about lost memory cells, it was about selling storage space in your
enhanced brain...

Re:Perfect for 64bit computing.

[selderrr]

eum, I don't want to disapoint you, but none of these is currently RAM bound. Current connectionst models require far more CPU power than memory to keep all nodes updated. Real-time is a distant future. Even non-realtime AI is currently more stupid then my 3 month old daugther.

Re:4 Bits in 8 States?

[chrish]

One bit for parity?

Re:I'm not sure

[PD]

In the old days, when the address was put on the bus, you had a bank of 8 memory chips that all read the same address off the same bus. Each individual memory chip would put the bit for that address on its data out line, which represented the 8 bit number at a particular address in memory. That's right, every time you read a byte from memory, each bit came from a different chip. Today, the packaging is different, but the concept is the same.

Word Size and Memory Addressing

[DonGar]

but don't you have to divide the bits (by 8) to get the bytes?

If memory were bit addressable, you would be correct. However most modern machines are byte addressable. That means that each memory address refers to a full byte.

It is perfectly possible to build machines that are only word addressable, where a word is 32 bits or 64 bits, or even larger. The advantage is that you can address more memory with a given address size. 32 bit words means address size * 4 bytes, 64 bit means * 8 bytes. The disadvantage is that you can't easily work with chunks smaller than the word size. Most current machines fetch and write at least a byte from memory, even when they are only reading or updating a flag of a single bit.

Since most folks are used to working with byte addressable, and there are no major reasons to change, I would expect byte addressable to remain the standard for a long time to come.