Microsoft Dropping Itanium Support For Clusters 265
upsidedown_duck writes "According to an article at TheStreet.com, Microsoft is opting not to support Itanium on its coming release of Windows Server 2003 Compute Cluster Edition. Instead, Microsoft will focus on AMD's offerings and Xeon."
The future of itanium? (Score:3, Informative)
This is actually an exciting opertunity for AMD since they can increase their margin in the sever and business arena where the big money is. They should seize this opportunity and start pushing their server lines.
Wrong... (Score:5, Informative)
Siemens and Bull (both major vendors in Europe), Dell, and IBM, and probably a lot more that I'm forgetting support ia64.
Actually pretty much every hardware vendor (that's traditionally worked with Intel CPUs) supports ia64 in one way or another.
But this article isn't a surprise. ia64 is just presently a pretty crappy CPU for clustered computing because it's very hot, sucks a lot of power and very expensive. When building a large cluster you naturally have to balance heat, energy and cost against performance much more than you do with most setups.
Re:The correct response: So what? (Score:4, Informative)
Not their high-end servers.
Re:Wrong... (Score:3, Informative)
FWIW, a Xeon uses slightly more power than an Itanium chip, and yes the Itaniums are very expensive. However, I believe that both of these are going to change. The Itanium already has a low power model at 1GHz, and Intel is looking at upping the speed of these low power offerings. And they better start reducing their prices.
And being that the current 2nd and 5th [top500.org] fastest clustered computers are based on the Itanium chip, ovbiously someone with more decision making power than you believes that these processors are OK for clustering. The first AMD offering is at #17.
Anti per-core-licensing and pro per-core-benchmark (Score:3, Informative)
Re:Oh great , the x86 arch. wheezes on a bit longe (Score:3, Informative)
Re:Wrong... (Score:4, Informative)
However Itanium is good for single image NUMA architectures. They can do things very well that clusters are very crappy at. And Clusters can do lots of stuff cheaper and faster then those big NUMA stuff comes from.
Itanium is being pushed increasingly into higher end computers. You know why Itanium is important?
Power970 cpu limit: 2-4 cpus
Opteron cpu limit: 8 cpus
Itanium cpu limit: 512 cpus.
SGI is being very successfull with it's 512 itanium machines running Linux.
That's 512 cpus with ONE OS running a single Linux 2.6 kernel. (series 2.4 kernels didn't scale well past 4 cpus, and hit a brick wall in performance at 16 cpus. In one revision from 2.4 to 2.6 turned linux into a viable supercomputer-level peice of software BTW)
For example that 2nd ranked "top500" computer is a 20 machine Beowolf style cluster. Each machine has 512 cpus.
SGI was able to build a 10,160cpu cluster in 4 months.
Hell when they started construction in less then 2 weeks they were running space shuttle simulations on it.
That's AS it was being built.
You can't do that with power970's. You can't do that with Opterons. Those Itaniums are not going anywere, and comparing them to Opterons and Power970's is a mistake. These proccessors are in completely different leages.
The Opteron and Power970 just doesn't compete with them. And remember that even though clusters are very impressive but are not suitable for many tasks.
It competes with the Sun Sparcs and IBM Power architectures. Currently IBM is dominating...
And to say that the cpu that runs the #2 ranked cluster (and completely dominates the highest ranked Power970 or x86 machine) is a crapy clusting cpu is just plain ignorant.
Personally I would think it's more of a indication of Microsoft's inability or lack of desire to support operating systems that run at this level. Windows always has and continues to be only a mid to low end operating system.
Re:Oh great , the x86 arch. wheezes on a bit longe (Score:3, Informative)
Here's what they've tried so far:
iAPX432: arguably the CISC of CISCs. Out-VAXED the VAX, the only instruction set more complex was one of the Japanese TRON designs.
i960: this one had a chance, it was a fairly conventional RISC with good performance, but it was too early. Intel was still enamored with the x86 architecture, and it got stripped of its MMU and shunted into embedded systems lest it compete with the x86.
i860: Baroque RISC variant that forced the compiler to do an incredible amount of work to get decent performance. Kind of a trial balloon for the IA64.
IA64: Even more baroque RISC/VLIW blend, instructions are basically RISC-like, but bundled together in wide instructions. Again, the compiler has to be insanely great. There are some insanely great compilers for it now, we'll see...
XScale: take the DEC StrongARM and give it the Intel touch: long pipelines, heavy dependency on the compiler, the 400 MHz XScale was not a lot faster than the 206 MHz StrongARM. It's still got a shot of taking market share away from x86 at the low end, except that other companies like VIA and Transmeta are waiting to take that on if Intel really starts trying to push.
If they really wanted to wean themselves from the x86 they'd have kept the Alpha EV8 team working on the Alpha, release it as the Intel AXP Architecture, and pretty soon people will forget that it's not their design.
I don't think Intel's managers really want to wean the company from the x86. They say they do, and may believe it, but their actions don't show it.
Re:Future (Score:3, Informative)
> design they bought.. however, they managed to
> cripple it beyond recognition....
The Itanium and its grandparents at HP were already in production by the time HP bought Compaq (which had previously bought DEC, the creator of the Alpha). HP did reassign many Alpha engineers to Itanium work, but that was widely believed to be a move to no-compete-prevent them from going to Fujitsu and continuing their work on Alpha.
sPh
Re:Any next generation chip left? (Score:2, Informative)
The Alpha's approach was simple ISA and high clock speeds. The initial versions didn't even have OOOE or byte addressing. It was the "RISCiest of the RISC". It wasn't until later versions when byte addressing and OOOE were added. The Alpha was a fine chip.
The competitor was the HP PA-RISC line which followed the lower clock speed but lots of execution units design philosophy (sound familiar to the AMD lines?) They found it very difficult to ramp up clock speed and very difficult to add more functional units (it's an x^^2 problem) so it stagnated pretty fast. Initially, the two CPU lines were similar in performance but the Alpha ran off from it readily.
Alphas were designed to be simple and high clock speed first, then add the complex stuff.
Alphas lack of volume was partly because instead of bin sorting the wafer, cores on the wafers were tested to see how fast they would run and sold as such. The high speed parts were only found a couple/few times per wafer so they were rare. In addition, this type of testing is very expensive in terms of time and resources to do (bin sorting is much cheaper) and also kept the cost of the CPUs very high for the time.
Re:Wrong... (Score:3, Informative)
Q1 this year, IBM sold 2 Itanium boxes. Yup, 2. Up to 200 by second quarter. IBM sells that many Power machines in about 6 hours. Dell shipped fewer than IBM; Bull shipped 80 but made more money than Dell ($5m versus $4m) Only HP, with about 80% of the ia64 market, shipped more Itaniums than Opterons. Even with Opterons selling for roughly 10% the cost of Itaniums, ia64 barely beat out Opteron in profits, and hasn't a prayer in Q3 and Q4.
The ENTIRE ia64 market for the first half of 2004 was a pissant $600m. 80% of which went to HP.
So, while you're correct that Siemens, Bull, IBM, Dell, etc. are major vendors, they're not major Itanium vendors, and wouldn't suffer a whit if Itanium died.
Re:Itanium is Linux bound (Score:3, Informative)
Re:Wrong... (Score:3, Informative)
A system builder is not limited by the processor architecture in how many processors can be added to a single system. If a company were willing to throw enough money at it, you could have a 32-way i386. It would be rather inefficient, as the i386 is not designed to make SMP systems efficient and easy to implement, but it could be done.
The limiting factor is the interconnect logic between the CPUs (and in software land, the OS).
The Opteron is in no way limited to 8-way systems; that is just the point at which a designer must add their own interconnect logic between the CPUs, because the 8xx series of Opterons "runs out of" Hypertransport links.
In fact, Sun Microsystems and Serverworks are collaborating on the creation of a 16-way and 32-way Opteron chipset" [amdzone.com].
Further, I would argue that the "Top500" list is fairly meaningless, because the only test they use to measure "performance" is Linpack. All Linpack does is solve linear equations and linear least-squares problems. You'll notice that Xeon systems are much faster than Opterons in this test. This does not model the real world, where Opterons have a clear performance lead in almost everything you can throw at them.
There was a discussion about this [storagereview.net] on StorageReview.com about this time last year. You'll notice the last post in the thread is to an article describing the inadequacy of the current supercomputer benchmarks, and an announcement that they plan to completely overhaul the system by 2006.
Not that you were defending the legitimacy of the Top500 list per se, but it was brought up in this thread, and provided an opportunity to bitch and moan about it without creating another boring message.