Nanotechnology Gets Finer

An anonymous reader writes "ZDNet reports on a new level of detail found in nanotech construction." From the article: "Japan's NEC Electronics has developed a technology to make advanced microchips with circuitry width of 55 nanometers, or billionths of a meter, the Nihon Keizai Shimbun business daily reported Sunday. Finer circuitry decreases the size of a chip and cuts per-unit production costs. It also helps chips process data faster."

Nanotechnology?

[Leomania]

We've had sub-micron CMOS processes for years now. Many of us are using computers with 90nm chips in them. But I've never heard of it called nanotech before. Maybe it's not inaccurate, but in my mind that term is more descriptive of other materials employing nanoscale materials that never did before (clothing comes to mind).

with decreased size...

[Anonymous Coward]

... comes increased RF interference and possible heat concerns, with more electrons flowing through the same amount of area.

What we need is chips that work smarter, not harder.

Re:Is there a limit?

[Anonymous Coward]

It's not about maths, it's about physics.

Of course there is a limit to how small circuitry can get. I'm no physicist, either, but I can't see how circuitry could get any smaller than an atom's width.

In other news

[contrapunctus]

Telescopes see farther, and batteries last longer.

BS Article

[Jason1729]

Chip fab size has nothing to do with nanotech.

Re:This sort of things always worries me

[kkek]

The only problem with that is that almost every new technology could possible be used for "evil" purposes. Does that mean that we should never invent new technology? No. Being careful is one thing, but stopping scientific progress because of paranoia caused by a science fiction show is something different.

Re:How does new technology cut production costs?

[TERdON]

It sure does raise cost, exactly as you say. But if you're making the components smaller, you'll be able to make the chips smaller, implying:

1) more chips in each wafer
2) assuming same density of defects in the silicon crystal, a higher yield rate, as there is a lower chance that there is an error in each chip, as the area of each chip gets smaller. (easy demonstration: take a paper, draw 10 random dots on it. If you then split the paper in 8 pieces the chance of having a dot on a specific piece of paper is bigger than if you split the paper in 16 pieces)

1) and 2) together means that even if your costs will rise, as long as your density of errors rises dramatically (it isn't supposed to), you'll be able to get a lot more chips per wafer.

Conclusion: Even if the costs per wafer rise, as long as the cost per chip sinks, it will be profitable business.

Lots of room but little control

[Ogemaniac]

Sure, we chemists can make all sorts of little tubes, balls, rods, pyramids, etc. Unfortunately, as you said, they are usually a mixture of many different sizes (and hence properties) as well as contaminated with all sorts of crap. The SEM and TEM pictures you see in the journals are assuredly the prettiest of the bunch.

Worse yet, we have almost no control over the arrangement of our little tinker-toys. At best, we can get them to sort-of line up or form some sort of regular lattice on a large scale, or using something like AFM manipulate one at a time in order to study it (of course, this is infeasible on a production scale). We are a long way from being able to arrange these parts on a mass scale in any sort of arbitrary, complicated geometry.

Re:Don't we already have 35nm processes?

[pla]

35nm is planned but hasn't actually been done yet. It's unlikely to help much either, because current leakage at those levels is being insane.

Although we might not gain anything by going below 30-35nm gates, don't overlook the huge fallout rate of current photolithography (if you can still call it "photo" when dealing with "soft" x-rays as the light source).

If you can produce, at your extreme limit, a 65nm feature, then trying to produce exactly 65nm features leaves almost no room for error. If, however, you can produce down to 5nm features, then you can manage 35nm features with a huge margin of error.

Thus, your fallout rate drops from the current of over 50% (or so I've heard - I don't know the exact figure), to very nearly zero.


The practicality of clock speed increases and heat/energy reduction aside, better photolithography (or whatever manufacturing techniques we eventually move on to) means higher yields of better quality at the same size.

Also, consider the fact that some parts of a modern CPU run a LOT faster than other parts - Compare addition with division, for example. Addition has taken a single clock (less, actually, but assuming a serial dependancy, you can't do better than one op per clock) for several generations now, while division still brings the CPU to a crawl. If you could make a full adder "fast enough" at whatever size optimizes energy consumption (90nm seems pretty good at the moment; 65 might waste more than it saves), while chewing through power to perform a division in fewer clocks with 15nm gates - That would both improve performance and save power at the same time.

Re:Where's the Nanotech?

[aXis100]

AFAIK, nanotech was origonally about the construction of componets from the atom and up.

Whilst we may be building small things, it's really still chemistry and lithography that we're tinkering with. Only a few scanning tunnelling microscopes are actually building anything one atom at a time.