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Supercomputing Hardware

Next-Gen Processor Unveiled 183

A bunch of readers sent us word on the prototype for a new general-purpose processor with the potential of reaching trillions of calculations per second. TRIPS (obligatory back-formation given in the article) was designed and built by a team at the University of Texas at Austin. The TRIPS chip is a demonstration of a new class of processing architectures called Explicit Data Graph Execution. Each TRIPS contains two processing cores, each of which can issue 16 operations per cycle with up to 1,024 instructions in flight simultaneously. The article claims that current high-performance processors typically are designed to sustain a maximum execution rate of four operations per cycle.
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Next-Gen Processor Unveiled

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  • I want one (Score:4, Insightful)

    by Normal Dan ( 1053064 ) on Tuesday April 24, 2007 @04:36PM (#18861013)
    But when are they likely to be ready?
  • Hm... (Score:5, Insightful)

    by imsabbel ( 611519 ) on Tuesday April 24, 2007 @04:37PM (#18861039)
    The article contains little more information than the blurb.
    But it seems to me that we called this great new invention "vector processors" 15 years ago, and there is a reason they arent around anymore.
    "Many instructions in flight"=="huge pipeline flushes on context switches"+"huge branching penalities" anybody?
  • by Anonymous Coward on Tuesday April 24, 2007 @04:38PM (#18861043)
    1. Copy some university press release to your blog
    2. Make sure google ads show up at the top of the page
    3. Submit blog to slashdot
    4. Profit
  • by DrDitto ( 962751 ) on Tuesday April 24, 2007 @04:47PM (#18861221)
    The EDGE architecture gets rid of relying on a single register file to communicate results between instructions. Instead, a producer-consumer ISA directly sends results to one of 128 instructions in a superblock (sort of like a basic block, but larger). In this way, hopefully more instruction-level parallelism can be extracted because superscalars can't really go beyond 4-wide (8-wide is a stretch...DEC was attempting this before Alpha was killed). Nice concept, but it doesn't solve many pressing problems in computer architecture, namely the memory wall and parallel programmability.
  • but... (Score:4, Insightful)

    by Klintus Fang ( 988910 ) on Tuesday April 24, 2007 @04:55PM (#18861353)
    The motivations for this technology provided in the article ignore some rather basic facts.

    They point out that current multi-core architectures put a huge burden on the software developer. This is true, but their claim that this technology will relieve that burden is dubious. They mention, for example, that current processing cores can typically only perform 4 simultaneous operations per-core, and imply that this is some kind of weakness. They completely fail to mention that the vast majority of applications running on those processors don't even use the 4 available scheduling resources in each core. In other words, the number of applications that would benefit from being able to execute more than 4 simultaneous instructions in the same core is vanishingly small. This is why most current processors have stopped at 3 or 4. Not because they haven't thought of pushing it beyond that, but because it is expensive, and because it yields very little return on the investment. Very few real-world users would see any performance benefit if the current cores on the market were any wider than 3 or 4. Most of those users aren't even using the 4 that are currently available.

    Certainly the ability to do 1024 operations simulatenously in a single core is impressive. But it is not an ability that magically solves any of the current bottlenecks in multi-threaded software design. Most software application developers have difficulty figuring out what to do with multiple-cores. Those same developers would have just as much (if not more) difficult figuring out what to do with a the extra resources in a core that can execute 1024 simultaneous operations.
  • Re:TRIPS (Score:4, Insightful)

    by glwtta ( 532858 ) on Tuesday April 24, 2007 @04:56PM (#18861371) Homepage
    I think it's mostly because the backronym is contrived and silly.
  • Re:Ix86 (Score:5, Insightful)

    by convolvatron ( 176505 ) on Tuesday April 24, 2007 @04:59PM (#18861409)
    you are absolutely right. no one should ever do any research into
    something which doesn't ultimately look like an x86.
  • Re:This is cool! (Score:3, Insightful)

    by treeves ( 963993 ) on Tuesday April 24, 2007 @05:05PM (#18861519) Homepage Journal
    If it's so cool, why did it take three years for us to hear about it? I'm really asking, not just trolling.
  • by Anonymous Coward on Tuesday April 24, 2007 @05:21PM (#18861773)

    A lot of this is due to the fact that most popular languages right now do not support concurrency very well. Most common languages are stateful, and state and concurrency are rather antithetical to one another. The solution is to gradually evolve toward languages that solve this either by forsaking state (Haskell, Erlang) or by using something like transaction memory for encapsulating state in a way that is easy to deal with (Haskell's STM, Fortress (I think), maybe some others).

    Concurrency is not that hard to do well in the right setting.

    And before anyone claims that Haskell and Erlang are impractical, there are many examples of "real world" programs written in them.

    A few nice, and very useful ones are Yaws [hyber.org] (for erlang) and Darcs [abridgegame.org] (for Haskell). There are many others (even quake clones), which I won't bother listing, but people can find them easily if they look.

    Regarding concurrency, and its ease of use in these languages, I'm taking a machine learning class at the moment where most of the problems are computationally intensive, and could stand for improvement by making use of multiple cores. I do all of my assignments in Haskell, and not only are my solutions often shorter than those of my classmates (and they often work fine the first time they compile), but it's usually trivial to allow my application to scale nicely to as many cores as I can throw at it. It's worth mentioning, by the way, that most algorithms given in these classes are given under the assumption that people are using imperative languages, and even then, it's still easy. It takes a while to learn how to approach problems differently without mutable state, yes, but it's not as hard as some people make it out to be. I think it has more to do with the fact that people just don't like to learn anything new unless they absolutely are forced to do so, which is a pity.

    By the way, there is a nice presentation [mit.edu] from Tim Sweeney on what he would like future programming languages to look like, and there's a lot in there about functional programming, concurrency, and expressive (re: dependent) types.

  • by Erich ( 151 ) on Tuesday April 24, 2007 @09:47PM (#18864381) Homepage Journal
    TRIPS, like many other projects optimized to produce the largest number of PhD students possible, starts out with a premise something like:

    So, I have this big array of CPUs/ALUs/Functional Units, all I need to do is program them and I can be the computingest damn thing you ever saw!

    And it's true. You build a sea of ALUs and you sic some folks on hand coding all sorts of things to the machine, and you end up with some spectacular results.


    The problem is that we still can't get a compiler to do a good job at it, for the most part. We thought we could, and we threw every bell and whistle into IA64
    for a compiler-controlled architecture, and you've seen what we've ended up with. Many years later, the situation is still pretty much the same: the compiler
    can't do all that great of a job with these sorts of machines.


    Don't get me wrong, there are lots of good ideas in TRIPS or any of the various other academic projects like it, but I'm yet to be convinced that it's useful in
    any kind of real codebase that's not coded by hand by an army of graudate students. For some tasks, that's an acceptable model -- It's been the model in the world of
    signal processing for quite a while (though becoming less so daily) -- but for most mainstream applications it just won't fly.


    That, and it's hard for compilers to have knowledge about history. It's terribly important for optimization, and it's just hard to get into the compiler (though relatively
    easy to get into a branch predictor).

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