100x Denser Chips Possible With Plasmonic Nanolithography

Roland Piquepaille writes "According to the semiconductor industry, maskless nanolithography is a flexible nanofabrication technique which suffers from low throughput. But now, engineers at the University of California at Berkeley have developed a new approach that involves 'flying' an array of plasmonic lenses just 20 nanometers above a rotating surface, it is possible to increase throughput by several orders of magnitude. The 'flying head' they've created looks like the stylus on the arm of an old-fashioned LP turntable. With this technique, the researchers were able to create line patterns only 80 nanometers wide at speeds up to 12 meters per second. The lead researcher said that by using 'this plasmonic nanolithography, we will be able to make current microprocessors more than 10 times smaller, but far more powerful' and that 'it could lead to ultra-high density disks that can hold 10 to 100 times more data than today's disks.'"

Re:Fragility

[wjh31]

brownian motion isnt really relevant at this level, but i imagine that if the channel or 'wires' or whatever were close enough then tunneling could be an issue, but probability of tunneling falls off exponentially with the distance, and the severity depends on the energy, but if the wires are put close enough then it could be an issue, however only if there was just few atoms between channels

Another maskless scanning lithography system

[Yarhj]

One of the difficulties with a scanning technology like this is throughput -- with mask-based lithography you can expose dice with great speed, while something like this will have to scan across the entire surface of the wafer. It sounds like there's good potential for parallelization (the article mentions packing ~100k of these lenses onto the floating head), so this technology won't necessarily be as slow as electron-beam lithography, but I can't imagine it'll be cheap either. Furthermore, the software and hardware involved must be much more complex than a conventional stepper; now you've got to modulate your light-source very rapidly, rotate your wafer, and keep track of the write-head's position to sub-nanometer precision. Tool design and maintenance costs will be pretty high, I imagine.

Re:Impact on Big chip manufacturers

[freddy_dreddy]

You have to make a difference between Fabs which produce ICs and companies that produce Fab equimpent. Off course they're intertwined but AMD and the likes is an architecture Co, where Companies like ASML drive Fab technology. The "slow rate" is set by industry agreements - milestones - to keep the cost of Fab tech R&D minimal. The shrink step is a factor 2 for surface, resulting in a factor sqrt(2) for feature size. Litho tech companies use this step because the market is not viable for developing Fab tech which takes a different approach: litho is just a fraction in the hundreds of steps it takes to produce an IC. If you were to implement a new Fab litho technique which differs from the roadmap you won't have customers because the technology isn't in sync with the other processes. In other words: this new technology is only viable if the others jump on the bandwagon, so far it's "only" proof of concept. The field of Fab tech R&D is filled with new concepts, but that's just a small part of the story.

Re:5-10 years

[Klaus_1250]

Arg, ... need to preview. nuclear fusion power-generation, that is.

Re:Finally, a use for Roland's dick

[philspear]

Not that it matters, but that's off-topic, not flamebait.

Re:Fragility

[drerwk]

I tend to think of Brownian motion happening in a gas or liquid - which Wikipedia confirms http://en.wikipedia.org/wiki/Brownian_motion [wikipedia.org]
Thermal diffusion of atoms in a device do cause problems and limit the temperature at which semiconductors can work. In fact, diffusion of dopants is one way a chip can 'wear out' with long term use. No doubt the smaller the scale the more problem diffusion will be, but it tends to be very temperature sensitive, so keeping the device at some reasonable temperature would prevent, or at least slow the problem.

Re:Impact on Big chip manufacturers

[Valdrax]

Do current chip manufacturers like Intel and AMD work on new lithography techniques, or do they focus more on architectural changes?

Yes. This research was funded by the National Science Foundation, a federal agency, but IBM, Intel, and AMD are all active in process technology research. I can't dig up much in the way of what they're currently researching, but here are a few things I was aware of in the past few years (and some things I dug while looking for them):

• Intel was researching extreme-ultraviolet (EUV) lithography around 2002-2004.
• Intel is also funding research into computational lithography to avoid having to do immersion lithography, like IBM and others are doing for the next generation.
• AMD & IBM were partnering on a test fab for EUV lithography in 2006 and had successfully demonstrated the ability to create transistors but were still working on metal interconnects at that time. I'd bet money they've gotten past that point by now.
• IBM did a lot of pioneering work on strained silicon that they announced back in 2001.
• Silicon-on-insulator (SOI) was another fab technology they pioneered in 1998, but it hasn't spread much in the industry beyond them, AMD, and Motorola / Freescale -- in other words, IBM and its partners.
• And then again, back to IBM, they were the first company to come up with a viable process for laying down copper interconnects, using what's called a dual-damascene process, in the late 90's.
• Hitachi has been actively developing electron-beam lithography for over a decade, but the technology has yet to really live up to its promise as a commercially viable competitor for photolithography AFAIK.

Some of the above research was about commercializing "pure" research done in independent labs like this experiment, but a lot of it was directly funded by the big fabrication companies and their clients and partners. Since I'm not in the fabrication industry myself, I can't really comment any further on who has done what (and how much each of the above deserves credit). This is just news I remember from years past.

Re:Fragility

[Gibbs-Duhem]

Tunneling electrons and other quantum effects are already in effect in current devices. We just design around those effects instead of taking advantage of them currently. When we really get the ability to make reliable 5nm size scale parts, we'll just switch to quantum dot based transistors (single electron transistors).

Brownian motion isn't relevent here.

A big issue is that sharp features are thermodynamically unstable (lots of dangling surface bonds), so edges tend to "soften" over time due to surface diffusion. Also, at ohmic contacts you can get pits forming which can eventually degrade features.

Another issue is that at the size scales we're talking about, current insulators stop working. They're looking at switching to a variety of new materials for this purpose (for example, IrO2), but these are tricky. This is what they mean when they say "high dielectric constant" materials. Every MOS transistors has a this oxide layer (between the Metal and the Semiconductor), and that layer's thickness defines many of the physical properties of the device.

Finally, you have to worry about inductors to a lesser extent. Current inductors aren't quite good enough, but we're working on that too =) Nanoscale metallic alloys are definitely the way to go.

In any event, this article is sort of sensationalist (surprise!). I was able to make 20nm features using physical embossing (stamping metal liquid precursors with a plastic stamp and then curing them) back in 2002. Making features of small size scale is easy, it's keeping error rate, making interconnects, etc that's hard and annoying. Plasmonics is very neat though, I can imagine it working with time.

Besides, hard disks already have magnetic domains of ~ only a few nanometers anyway.

Re:Fragility

[mehtars]

http://www.extremetech.com/article2/0,1697,1994121,00.asp [extremetech.com]
Here is an article on it. Although its from 2006, there has been more work done on it. There are more articles on it in the literature.
If you search for 'self healing' microprocessors you can find a number of articles on it.

Re:Another maskless scanning lithography system

[TubeSteak]

so this technology won't necessarily be as slow as electron-beam lithography, but I can't imagine it'll be cheap either.

You obviously didn't RTFA.

Modern 40/45nm and the upcoming 23nm chips need very short wavelengths to get produced.
This is expensive.

The new technique uses relatively long ultraviolet light wavelengths.
This is very cheap.

The researchers estimate that a lithography tool based upon their design could be developed at a small fraction of the cost of current lithography tools.

Space elevators

[Hal XP]

Don't forget the space elevator, which, according to the late Arthur C. Clarke will get built 50 years after [nasa.gov] it stops getting modded funny.

Not true

[Anonymous Coward]

This is completely untrue, if a transistor fails on a CPU, that's it, there's no routing around the damage as you seem to imply.

If you'd actually read the article you referenced when queried by someone else, you'd see that was a three year study initiated in 2006, so even if that study bears fruit it'd be 5-10 years at least before it showed up in the CPUs you buy from Intel or AMD.

Tunneling/Quantum effects: ~10nm

[GanjaManja]

the researchers that make 200-400GHz transistors today DO in fact worry very much about tunneling. (I'm thinking of InP/InGaAsP transistors)

Quantum wells are around 5-10nm wide, so anything approaching ~20nm would at least have to account for that sort of quantum effect. So density may have a difficult limit to breach, but smaller lithography certainly makes high speed transistors easier to implement on CMOS.

(EE, not physics)