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Technology Hardware

Raspberry Pi PCB Layout Revealed 112

Posted by samzenpus from the final-design dept.
An anonymous reader writes "Yesterday, the final Raspberry Pi printed circuit board (PCB) layout was revealed. The word 'packed' comes to mind as this is one very complicated looking board. The reason for that is just how much Raspberry Pi has strived to save money on the machine by using complex routing to keep things small and cheap. The Raspberry Pi team don't believe the design is going to change again unless they missed something. With that in mind, they revealed the final board is exactly the same size as a credit card, measuring 85.65 x 53.98mm."
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Raspberry Pi PCB Layout Revealed More

Raspberry Pi PCB Layout Revealed

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  • Screen and keyboard? (Score:5, Funny)

    by lordmetroid ( 708723 ) on Tuesday November 15, 2011 @06:20PM (#38066654)
    How am I going to use this computer without a screen and keyboard?
    I demand a credit card sized keyboard and screen!

  • Comment removed (Score:5, Insightful)

    by account_deleted ( 4530225 ) on Tuesday November 15, 2011 @06:32PM (#38066818)
    Comment removed based on user account deletion

    • Re:Complicated? (Score:5, Informative)

      by Austerity Empowers ( 669817 ) on Tuesday November 15, 2011 @06:53PM (#38067094)

      I would go as far as to say that looks like one of the simplest and least complicated designs I've seen. Also it should be noted that small and cheap compete with one another. Cheap things they that cost space- fewer routing layers (components & traces often need to be farther apart for impedance & via room), using larger components (0402 or bigger generally), not using blind/buried vias, using routing space for power. Small things they did that added cost- front/back side assembly, through hole components on a mostly SM design.

      It looks like a fairly simple design. I'd try to get rid of the through-hole stuff unless it's just debug, that adds a step in mfg which can raise cost and also causes place keepouts to eat up valuable real-estate.

      The post should have raid "Board layout review, all slashdotters attend".

      • Re: (Score:2)

        by kmahan ( 80459 )

        Did they length match any of those pairs? It'd be interesting to see a trace length report.

      • Is there a layer-by-layer break out some place? The way they have all the layers on top of each other in the PNG makes it very hard to tell what's going on in the red-colored layer. The yellow layer at least looks pretty simple, though the fact that the QFN's epad doesn't appear to be grounded strikes me as a bit questionable. A lot of IC's rely on downbonds to ground internal pads. Leaving them floating is a big no-no. While they'll probably find alternate paths to ground, they're not the sort of path

        • Re:How can you even tell? (Score:5, Informative)

          by Savantissimo ( 893682 ) on Tuesday November 15, 2011 @11:11PM (#38069716) Journal

          Most of those questions are answered in the comment thread on the article. No individual layers released until their PCB designer gets back. The picture shown does not include power or ground planes, so the missing ground is likely hidden. The connectors being used will require some through-hole components. The GPIO headers will be on the final release, but unpopulated.

          The biggest omission to my mind is the lack of mounting holes or other fixtures. (I'm not sure where you see "plenty of empty space". Even getting screw holes to fit would require some thought, it seems to me.) The screenshot was also pretty useless for determining the exact mechanical placement and dimensions of the connectors, which is the only important thing for those designing cases. Someone in the comment thread did mark and label the rough outlines of the connectors, though. The connector placement also seems not at all designed for usability, or with any thought to future case design but purely to make the cheapest possible board.

    • Re:Complicated? (Score:5, Informative)

      by mla_anderson ( 578539 ) on Tuesday November 15, 2011 @06:54PM (#38067108) Homepage

      Actually looks pretty slack with lots of space. However to make it inexpensive requires much more care in the design rules and routing. Placing and routing a board with tight component clearances and tight trace and space is easy and expensive. Taking the same components on a small board from 0.1/0.1mm trace and space to 0.15/0.15mm trace and space takes a lot of work, but can significantly reduce the cost to manufacture.

      From an initial view, the biggest cost adder I see is components on the solder side. There don't seem to be too many on the bottom side and with a bit more work it could probably be made into a single sided board. I'm working on a cost sensitive board right now, and one of the big things we've done to cut cost is make sure all components are on the top side. (Low cost is relative, this BOM is many many times the projected price of the R-Pi.)

      • Re:Complicated? (Score:5, Insightful)

        by ebenupton ( 2424660 ) on Tuesday November 15, 2011 @07:01PM (#38067192)

        Would be great to get all the components on the top side. Unfortunately, you pay for that in extra track length between the SoC decoupling caps and the BGA balls. I believe Beagle and Panda both do this with their OMAPs, and (mostly) get away with it, and we may investigate it in a later revision; in general departing from datasheet recommendations makes me queasy, even for a chip I worked on...

        • Re:Complicated? (Score:5, Informative)

          by mla_anderson ( 578539 ) on Tuesday November 15, 2011 @09:36PM (#38068846) Homepage

          Generally if the small caps are close to the package and tied to planes (I'm assuming there are planes) with short thick ties to reduce inductance you can get by with it just fine. The bulk caps can be quite a ways away as long as they are also tied directly to the planes. We're running some very high speed stuff this way without problems. Xilinx has some good info on bypass caps and how they can be placed in their Spartan 6 docs.

          If there's no planes then you have to have the relatively thick tracks already for current carrying capability, but the inherent inductance could possible give you an edge in filtering as long as you're not yanking the individual pin levels out of tolerance.

          • Xilinx has some good info on bypass caps and how they can be placed in their Spartan 6 docs.

            Xilinx Application Note 623 [xilinx.com] is an excellent introductory guide to PDS design.

            Just to expand on your points: the main thing to bear in mind is that the higher the frequency you're running it, the smaller the cap values you need and the more important it is to keep loop inductance low. There are two cases in which I place my decoupling caps on the reverse side inside the package footprint (usually BGAs have an area free of pins in the centre of the die). Firstly, when I'm running at very high frequencies (

    • This machine is the spiritual successor to the BBC Micro. I have here the BBC Micro User Guide, which has hand-drawn circuit diagrams in the back. In comparison, this board is very complicated. In comparison to anything modern, it's pretty simple.

    • Re:Complicated? (Score:4, Interesting)

      by muon-catalyzed ( 2483394 ) on Tuesday November 15, 2011 @07:49PM (#38067804)
      Except nobody noticed that it is just one extended socket for the massive proprietary Broadcom BCM2835 chip (SoC) that provides pretty much everything, so this is 90% Broadcom thing, the UK team just provides fancy packaging and folklore. Does anybody know the price point of that Broadcom silicon?

      • The announced price is low enough that I don't really care how much the raw chip costs; for hobbyists, you're very unlikely to find a better deal.

        What concerns me more is the "proprietary" aspect. How many of the chip's features will be accessible by hobbyist developers? Will we be receiving full public documentation on how it works?

        • Re: (Score:3, Insightful)

          by rec9140 ( 732463 )

          "What concerns me more is the "proprietary" aspect. How many of the chip's features will be accessible by hobbyist developers? Will we be receiving full public documentation on how it works?"

          No, getting data sheets from most silicon makers today, is tanamount to asking for state secrets,err...ok not such a good example, well not hapenning... and don't mention to the Pi people.

          See:

          http://www.raspberrypi.org/forum?mingleforumaction=viewtopic&t=1077 [raspberrypi.org]

          • No, getting data sheets from most silicon makers today, is tanamount to asking for state secrets,err...ok not such a good example.

            And asking for answers from Broadcom if you're not buying millions of their chips is likely to get you shot for treason.

      • Re: (Score:3, Informative)

        by mirix ( 1649853 )

        It doesn't really matter what the chip costs alone, as you won't even get a fucking pin diagram out of broadcom without a large order and an NDA.

        • Yeah I'm pretty bummed that they chose Broadcom. It's ARM, and there's plenty of vendors.

          I'm just guessing, but perhaps another more "open" choice would have added $10 to the cost, and maybe they didn't want to go there, if their price target
          was firm.

        • Re:Complicated? (Score:5, Interesting)

          by Savantissimo ( 893682 ) on Tuesday November 15, 2011 @11:20PM (#38069794) Journal

          Yet other manufacturers don't take that attitude. Go look at TI or Analog devices. Full datasheets right there, often running to hundreds of pages reasonably priced development boards, often free samples. Broadcom claims to have features such as DSP and GPU built in to this chip, but I don't know what use they are supposed to be if they are totally undocumented. Supposedly about 98% of the FLOPS in this thing are in the GPU, but good luck getting at them.

          • Re: (Score:1)

            by Anonymous Coward

            Atmel is pretty good about full datasheets, too; that's probably one of the reasons the Arduino people went with them. I'm not a big fan of Broadcom either.

          • Although TI are a lot more forthcoming with datasheets they will still hold back information on things like the DSP core inside an ARM SoC. So you get DSP based codecs as binary blobs and no information on how to target the DSP yourself. And then further up, in the same family, you'll get a similar processor that *does* have an accessible DSP core... but you have to pay for the privilege in chip cost (and it only makes sense to do that if you actually need that feature).
            Then again, as you said, TI are good

  • complex routing ? (Score:5, Insightful)

    by alvieboy ( 61292 ) on Tuesday November 15, 2011 @06:34PM (#38066850) Homepage

    At first glance, this looks like a normal routing with a 4-layer board. Eventually 6, if you add proper ground + power.

    There's nothing indicative of PCB parameters, like drill sizes, clearances, blind/buried vias, minimum trace width, so on. Again, a simple look reveals nothing but common parameters for PCB.

    Again, TFA is biased.

    • I'm with you on this. It looks to me that someone took time and care over it to keep the tracking to a minimum but not anything special. I have a draw full of PCBs which are similar and I don't claim to be particularly good at PCB design.

      • Re:complex routing ? (Score:5, Informative)

        by ebenupton ( 2424660 ) on Tuesday November 15, 2011 @07:06PM (#38067288)

        As I understand it, the biggest challenge was escaping a 0.65mm BGA without using significant amounts of HDI on a 6-layer board, while keeping good solid power and ground planes and large (i.e. cheap) track and gap specs. Relax more or more of those and it is indeed trivial - our alpha boards were done in about four days by doing exactly that.

        • Out of curiosity, how much more expensive would smaller track and gap specs be for similar volume? No need for an exact number

          • Re:complex routing ? (Score:5, Informative)

            by ebenupton ( 2424660 ) on Tuesday November 15, 2011 @07:51PM (#38067826)

            Off the top of my head, we save around a buck at 10K-off through a combination of 6 layer, coarser T&G and limited HDI. Figures for UK manufacture; YMMV in elsewhere, particularly in the far east (where cutting edge volume manufacturing is much easier).

            The particular stack-up we've chosen is only one possible cost minimum; I've heard it suggested that 8 layers with zero HDI is quite competitive for 0.65mm BGA.

          • Another cost is wastage. As trace and space get toward the manufacturer's minimum recommended numbers their yield goes down and therefore their price goes up.

    • Yeah, nothing to see here (coming from someone who essentially designed an ARM Linux system-on-board with similar performance for an entirely unrelated application)...ordinary and almost reminiscent of reference designs. The CraneBoard is much more complex.

    • Looks pretty pedestrian to me (although a BGA breakout on so few layers is worth a tip-of-the-hat). I think I only see three signal layers; blue, yellow, and reddish-brown. So they probably have a proper ground plane that's being excluded from the pic. The big swaths of yellow might be a power bus.

      Now with only one solid plane, one of the other three layers will not have a solid reference plane. Did the designer take time to make sure no high-speed signals run on that layer? If not, then I expect a noi

      • Re: (Score:2)

        by dotbot ( 2030980 )

        Looks pretty pedestrian to me (although a BGA breakout on so few layers is worth a tip-of-the-hat). I think I only see three signal layers; blue, yellow, and reddish-brown.

        Is blue really a signal layer? Looks like blue and pink are silks to me and the board is simply double-sided.

    • Re: (Score:2)

      by artor3 ( 1344997 )

      I don't know know what you're looking at, but it's pretty clear to me that this is a 2-layer board, unless you're counting silkscreens as layers, which would be really weird.

  • Also that size... (Score:5, Interesting)

    by X86Daddy ( 446356 ) on Tuesday November 15, 2011 @06:34PM (#38066856) Journal

    Penguins and Altoids tins happen to be about that size as well... I wonder how well a populated Pi will fit... if so, awesome little PC cases!

  • Not so packed (Score:4, Informative)

    by dpaton.net ( 199423 ) on Tuesday November 15, 2011 @06:41PM (#38066942) Homepage Journal

    Really, it's not. I do stuff like this every day. It looks pretty normal for a 4-6 layer board with a BGA or two on it. TFA needs to learn about what modern design standards are. It's only complicated if you still lay boards out with ruby tape or a sharpie.

    • I think they meant to say: "It's really complicated compared to the average DIY Arduino shield with DIP sockets on it."

      • Re: (Score:3)

        by inflex ( 123318 )

        The trouble with this sort of reporting is that it betrays the work done daily by people who really -are- dealing with complicated stuff. Reminds me of parents rabbling on about their "genius child" because the kid installs software O_o.

      • Yes, compared to something about 3 orders of magnitude less complex, this seems complex.

        However, I do 4 layer boards with the bigger AVRs and boards produced by BatchPCB 2 or 3 times a year. Its not really complex. I admit, I've not done BGA layouts, but with multiple layers I can't imagine it'd be THAT hard. Tedious to do by hand, certainly, but with software, meh, not much different than an excel spreadsheet really.

    • It's a pretty trivial board. I'd quote at most a day's work (8-10 hours) for a board of that complexity, even assuming I was handrouting the whole thing...

  • If I could ever easily design a non-expensive Sci-Fi armor suit that has redundant, networked computers, streaming video-to-internet from a helmet, real-time video display in helmet, easily detachable web cam/mic/speaker modules that can be used on or off armor, and able to be worn from -50C to +50C I would build it for my Halloween costume and stream visiting Halloween parties to a web page. Reusable for comic and anime cons too. Heh.

  • Comment removed (Score:5, Informative)

    by account_deleted ( 4530225 ) on Tuesday November 15, 2011 @07:30PM (#38067576)
    Comment removed based on user account deletion

    • Re: (Score:3, Interesting)

      by Jamie Lokier ( 104820 )

      all the software is "open" yet obfuscated

      The entire Raspberry Pi depends on a gigantic proprietary blob from Broadcom [elinux.org].

      So let's do a Nouveau-style reverse engineering project. How hard can it be?

      Sounds like a perfect project for the target audience: curious and talented kids. With a bit of experienced help if they get stuck (seems unlikely to me though, with sufficient time & motivation). Some kids love reverse engineering. I did when I was young and I was far from the only one (but we didn't have an internet to meet each other back then).

      (I did loads of reverse engineering from about age 11+ (that was 1983), starting

      • Elite ran in 14k of memory (which should have been enough for anybody, wokka wokka). This blob is 16 megs. That's a 1,170 11-year-olds; if they went about it with your methodology, they'd be printing out one disassembled line a second for about twelve weeks... And then they gotta figure out what it DOES. And all of this before Raspberry Pi changes CPU revs and the disassembling must start all over.

        • Re: (Score:3, Interesting)

          by Jamie Lokier ( 104820 )

          The bit about my own history was just to illustrate that young people (the target audience for RP apparently) do take an interest in that sort of thing, not to suggest a method! Of course nobody would use that approach any more! (The Elite reference was because David Braben co-authored Elite and is also involved in RP).

          If analysing the blob statically, and if you know the instruction architecture, we have much better tools now, including disassemblers, decompilers, type inference and much more. And inter

    • Re: (Score:2)

      by mirix ( 1649853 )

      I had a lot of hope for this, and was willing to accept a binary blob on the GPU, for the price. Don't think I'll need video anyway.

      But having to load a binary blob on the GPU in order to load a (bootloader | kernel)? Yuck.
      I guess that's better than the driver though, in a way, as it shouldn't be kernel dependent, like a closed BIOS on a motherboard... So you don't have to worry about not being able to run the board with linux-5.8 as that is neither here nor there. (at least, this [booting] portion. You'll

      • Re: (Score:2, Troll)

        by BitZtream ( 692029 )

        You''re upset because you have to load a 'binary blob' at boot ...

        Yet you're too stupid to realize that the chip itself contains several embedded 'binary blobs' that it uses to get to that boot loader.

        You're basically bitching about something that happens in every microprocessor on the planet, the only difference being that you have to help out in this one, where as say a pentium chip has the blob built in.

        Same is true for video drivers. You Linux/GPL zealots get so fucking worked up up about binary blobs,

    • Re: (Score:1)

      by Anonymous Coward

      More info on this:
      http://www.raspberrypi.org/forum?mingleforumaction=viewtopic&t=1018 [raspberrypi.org]

  • Embiggen... (Score:3, Informative)

    by linatux ( 63153 ) on Tuesday November 15, 2011 @07:37PM (#38067680)

    a perfectly cromulent word

  • XBMC (Score:1)

    by Anonymous Coward

    XBMC is working on a port. That could make a big difference.

    I personally would like emulators.

  • What's in a Master Card? (Score:3)

    by Ostracus ( 1354233 ) on Tuesday November 15, 2011 @09:39PM (#38068876) Journal

    With that in mind, they revealed the final board is exactly the same size as a credit card, measuring 85.65 x 53.98mm."

    And it's name will be Selma [wikipedia.org]

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