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Intel Supercomputing Upgrades

Intel Announces Xeon E5 and Knights Corner HPC Chip 122

Posted by Unknown Lamer
from the one-treeleeon-flops dept.
MojoKid writes "At the supercomputing conference SC2011 yesterday, Intel announced its new Xeon E5 processors and demoed their new Knights Corner many integrated core (MIC) solution. The new Xeons won't be broadly available until the first half of 2012, but Intel has been shipping the new chips to a small number of cloud and HPC customers since September. The new E5 family is based on the same core as the Core i7-3960X Intel launched Monday. The E5, while important to Intel's overall server lineup, isn't as interesting as the public debut of Knights Corner. Recall that Intel's canceled GPU (codenamed Larrabee) found new life as the prototype device for future HPC accelerators and complementary products. According to Intel, Knights Corner packs 50 x86 processor cores into a single die built on 22nm technology. The chip is capable of delivering up to 1TFlop of sustained performance in double-precision floating point code and operates at 1 — 1.2GHz. NVIDIA's current high-end M2090 Tesla GPU, in contrast, is capable of just 665 DP GFlops."
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Intel Announces Xeon E5 and Knights Corner HPC Chip

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  • by Anonymous Coward on Wednesday November 16, 2011 @02:27PM (#38075972)

    Odds are... they have it lined up such that... they are in a 5x10 grid. Or a 5x5 Grid front/back.

    Just because it's a computer doesn't mean it's bound by the power of two. Boards are rectangular. Chips laid out aren't necessarily in binary distribution.

  • How can that be? (Score:4, Insightful)

    by gr8_phk (621180) on Wednesday November 16, 2011 @03:16PM (#38076580)
    A 50 core chip at 1GHz is going to need to perform 20 double precision floating point ops per cycle per core to achieve 1Tflop performance. OK, so 1.2GHz cuts that down to 16flops/clock. Since when can anything Intel Architecture achieve that many flops per cycle? Two 4-element dot products is only 14 flops. I suppose if they did two vector-scaler multiply-adds that would get 16 flops per cycle. So I just answered my own question. But can they really keep the FP unit running continuously at that rate? On all 50 cores?
  • by gstoddart (321705) on Wednesday November 16, 2011 @04:01PM (#38077144) Homepage

    No, it means you're an idiot who cannot deal with the fact that the prefixes have a specific meaning unless one is talking about computer

    So, are you always an asshole, or just on Slashdot?

If a camel is a horse designed by a committee, then a consensus forecast is a camel's behind. -- Edgar R. Fiedler

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