Project Aims To Build a Fully Open SoC and Dev Board 47
DeviceGuru (1136715) writes "A non-profit company is developing an open source 64-bit system-on-chip that will enable fully open hardware, 'from the CPU core to the development board.' The 'lowRISC' SoC is the brainchild of a team of hardware and software hackers from the University of Cambridge, with the stated goal of implementing a 'fully open computing eco-system, including the instruction set architecture (ISA), processor silicon, and development boards.' The lowRISC's design is based on a new 64-bit RISC-V ISA, developed at UC Berkeley. The RISC-V core design has now advanced enough for the lowRISC project to begin designing an SoC around it. Prototype silicon of a 'RISC-V Rocket' core itself has already been benchmarked at UC Berkeley, with results results (on GitHub) suggesting that in comparison to a 32-bit ARM Cortex-A5 core, the RISC-V core is faster, smaller, and uses less power. And on top of that it's open source. Oh, and there's a nifty JavaScript-based RISC-V simulator that runs in your browser."
expecting performance from IE? (Score:3, Insightful)
Are you expecting high performance from Microsoft IE, in their JScript engine?
One of the reasons Chrome EXISTS is to provide a high performance platform for Google Docs, Gmail and similar large JavaScript applications. These are the applications that intend to replace Microsoft' s cash cow, Office. It would be better for MS to stop shipping IE at all than for them to provide an excellent platform in which to run Google Docs.
Re:Where are those chips baked? (Score:4, Insightful)
From the article they are using TSMC [tsmc.com], which is one of the largest silicon foundries (ASIC manufacturing) in the world.
As for the all out open-source, they also make clear on the project page that hardware patents on the chipset instruction is supposedly strangling innovation for processors. I'm not sure I buy that, ARM, Intel and IBM have moved their architectures along pretty well. Even poor little MIPS has made strides despite losing market share.
Big names involved- RISC creator, rPi leaders (Score:4, Insightful)
For those who didn't read TFS, the project is led by people with a track record of getting things done. One team member helped design, and named, the RISC architecture. Others are leaders of the Raspberry Pi project. That suggests these people know how to do this sort of thing successfully.
Re:linux (Score:3, Insightful)
Yeah. That's not good somehow.
Based on the reported IPS of the RISC-V CPU emulator, it takes 1839 actual hardware instructions to cycle the RISC-V once.
So? The speed of an emulator isn't a reflection on the quality of a CPU. A cycle accurate simulator is designed to function exactly like the real thing in simulated time, not real time. It doesn't reflect either way on the actual silicon.
A better (but still poor) proxy for the performance of a CPU design on silicon is it's elaboration in an FPGA. The generator should be out real soon (I am not affiliated with the project, but it says on the github), then you can test it out on your FPGA board.
Unfortunately without a $250k (I'm guessing) or academic license, you can't elaborate a Cortex A5 for comparison, and neither core design seems like it is optimised for FPGA, so once again a poor comparison, but at least a fair one.
As a practical matter, a mask set at 40nm costs around $60k*, so an opensource SoC implemented on a closed source FPGA is still more open from a practical matter for me than an ASIC which I have to use expensive closed source tools to tape out and pay $60k* each time I run a "build".
-puddingpimp
* Maybe this number comes down through wafer sharing ala MOSIX.