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Diagonal Design For Chips 81

Posted by Hemos from the seeing-things-at-an-angle dept.
A reader writes "Simplex and Toshiba have a new design tool that allows circuits to run on diagonals. They're calling it X Architecture. Applied Materials, KLA-Tencor and DuPont Photomasks have signed on according to the press release. They're claiming 20% less 'wire', 10% faster, 20% less power and 30% better yields. Here's an EET article."
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Diagonal Design For Chips More

Diagonal Design For Chips

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  • Only 45? (Score:1)

    by Anonymous Coward
    Thanks, but I think I'll wait until they've cranked that up to 180 or 360 degrees. Such a small increment hardly seems worth it.

  • Perhaps it's just me, but I'm not all that excited about this. One of the key things to highlight is that this is just a tool and a method for doing 45 degree angles on chips.

    If companies can manufacture such devices reliably with high yield, the approach would achieve an engineering trifecta: higher performance, improved real estate utilization and lower power consumption.

    The word in the above statement is IF. That's a big if. Just because you can design something doesn't mean that you can fabricate it.

    As an interesting little side now, it should be noted that some of the people working on good old Magic are trying to implement non-manhattan geometries in it also. Although, doing it on a router would be kinda tricky.

  • Hasn't this already been used for a while in several fab houses?

    When I went through Comp. Eng. undergrad, I was told that there were two layout styles used in industry. "Manhattan rules", which forced all edges in the layout to be horizontal or vertical, and "Brooklyn rules", which let you use diagonal edges as well.

    The high-level synthesis tools won't care - they're just manipulating gates from the cell libraries, and letting the place-and-route tool worry about layout.

    The place-and-route tool would have to be tweaked to allow diagonal lines, which would be a substantial undertaking, but hardly earth-shattering.

    The cell libraries would have to have modules implemented that took advantage of the layout rules, but you have to make new cell libraries for every new process anyways.

    The lithography process itself doesn't care what design rules you use. It just forms images that have a certain minimum feature size and certain mask positioning tolerances.

    If Brooklyn rules really are used in industry, then these tools already exist.

    I'm just trying to figure out what's "news" here. (Maybe mixing the two rules methods, which is a fairly neat trick to help those stuck with Manhattan libraries.)

  • Hardly a Breakthrough (Score:5)

    by HardCase ( 14757 ) on Tuesday June 05, 2001 @09:21AM (#175073)
    Sure, it's a good idea...a straight line beats a 90 degree angle most of the time, but I think that the real breakthrough in this case is the potential for Simplex to make a lot of money in licensing fees to radically redesign the tools that we use to design and manufacture chips.

    Since the architecture isn't going to change on the top layers, where most of the action is, the improvements become incremental. It would be nice, though, to be able to shorten long interconnect runs, especially with capacitance becoming a significant issue now. But I wonder if the significant cost to replace existing design and manufacturing tools is worth the seemingly small gains that the technology offers.

    -h-

  • The problem I see with using fibre for chip-interconnect is that you need circuitry to change electrons to photons and vice-versa, which would add to the die-size significantly. You'd also introduce a delay while the photon/electron conversion happened. At the trace lengths that are on today's chips, that delay would likely negate any advantage in speed. There would be gains in electical isolation (interconect crosstalk), however.

    BTW, fibre carries a lot more data because it can use different frequencies (multimode fibre) and doesn't suffer electrical attenuation at higher frequencies. I don't think you'd be able to use multi-mode fibre on a chip without needing serious power and realestate. The only place I could see an advantage to fibre in a chip would be to interconnect a CPU to a large, full speed off-die L1 cache. But, IANACS (I Am Not A Computer Scientist).

  • ...and both to be hit with a suit from X.Org [x.org].

    Another LHA (Lame Humour Attempt) brought to you by the letter X.

  • You mean like Doritos?

    Mmmmmm...

    --
  • I don't know how to multiple the factors together but, "20% less 'wire', 10% faster, 20% less power and 30% better yields", isn't just 10%.

    Perhaps this improvement will be required to meet Moore's Law.

    --
  • I think that the distance savings is so little because how often can you make a diagonal connection? Obviously it will have to be done on a different layer than the 2 points you are connecting. But that layer will have its own pathways already that will have to be worked around.

    If you run every pathway at a diagonal you have just rotated the whole chip.

    I wonder if alternating layers at 45 degrees from eachother could be helpful.

    --
  • When I first saw the title, I saw "diagonal" chips, and in my mind, I imagined layers of silicon wafers stacked in 3D like //// with interconnections between layers running \\\\.
    Hey, I've already got this! Of course, my tower keeps tipping over.
    --

  • ummm... (Score:1)

    by JBv ( 25001 )
    does it work if i tilt my duron 45 degrees?
  • They must've been getting some shitty yield numbers! Maybe they should work on their manufacturing discipline first.
  • Less power and better yields are a big deal, because those properties don't scale with Moore's Law - quite the opposite.

    And even though diagonal wiring might seem like an obvious idea, I bet developing good routing algorithms that can take advantage of it is not easy at all. Most of the interesting problems in circuit interconnection are NP-complete.

    The routing algorithms have been around to do this well for years - they're mostly based around simulated annealing.

    Simon
  • If you think about how God would design a chip, obviously God would use curves.

    I'm surprised no one told you to look inside your head to see what kind of computer God would design. :)
  • >But, IANACS (I Am Not A Computer Scientist).

    Or, more appropriately, a Computer Engineer...

    --

  • Hmmm (Score:1)

    by hattig ( 47930 )
    Can I patent the cunning rotation by 22.5 degrees for layers 5, 6, 7 & 8 of those chips that have too many metal layers for their own good?

    Or even my cunning "Suss out the best angle of rotation for all metal layers 3+" method? Meaning that if 37 degrees in one direction is better than 45 degrees, then that is used?

  • Actually, routing algorithms would be the same as before. It is only a 45 degree rotated manhatten layout anyway.

    Layer 4: \\\\\ 135 degree
    Layer 3: ///// 45 degree
    Layer 2: ----- 90 degree
    Layer 1: ||||| 0 degree

  • It seems remarkable to me that just because people
    cannot fathom the reason why something is designed
    in a counterintuitive fashion it means that either
    a god did it for some inscrutable reason or because
    it's inherently wrong.

    Who the fuck made the earth round? It would be a
    lot simpler if it was flat. It took a little while
    to figure out "why" ... and we're still quibbling
    over the mechanism.

    It seems a little odd that vertebrates, with their
    "handicapped" visual inputs, have then gone on to utilize
    them in such a dramatically more aggressive fashion.

    I mean, of all the sensations that my species would get
    rid of first, I'd bet vision would be damn near last.
  • How would you have designed your eyeballs so they
    wouldn't have been so lousy?

    Did you know, perhaps, that the shape and internal
    structures of said cells may help to eliminate
    internally reflected, and therefore from a non-
    predictable source, light? Similar to an MRI,
    you might say.

    There even appears to be a creationist
    web-page arguing for the design of our eyes ...

    http://www.trueorigin.org/retina.htm

    They assuredly have some facts in there.
  • You're exactly right.

    When I was a co-op at Texas Instruments in 1992, their chip layout tool allowed for non-manhattan layout of any chip features and had done so for about 10 years (since the time layout was done by hand with colored pencils on acetate sheets).

    The change, if any, has to be to the automated routing algorithms, finally allowing them to take advantage of something besides north-south, east-west metal lines. This is generally hard because placing one wire in a metal layer essentially prevents you from placing local wires in any other direction (think 2 dimensional). A north-south wire blocks east-west wires, so you use a different metal layer for the east-west wires and connect them to the north-south wires with vias (holes in the insulating layer between the metal layers). One decent sized diagonal wire blocks both north-south and east-west wires in the entire layer, and in 1992, having a three metal layers (instead of two) seemed like an expensive luxury.

    The use of two of five metal layers for diagonals and then informing the routing heuristic of these additional "half-dimensions" could easily result in the incremental performance gains being discussed. But only incremental. The hype level in the article was certainly excessive, but that's marketing's job...

    As for the technical problems you mentioned, fabrication processes have certainly changed since I was last in hardware (1995), but even the mask cutters back then could rotate the mask plate to get straight lines cut in any direction they darned well pleased.

    One of the coolest examples of diagonal lines I saw while working there was a 6 transistor SRAM cell that had transistors and wires going in all directions. Tiled into a RAM array, it looked like a crystal matrix.

    Regards,
    Ross


  • To Simplex, that means shorter wires. By its own estimates, wire length is reduced by 20 percent on average using diagonal interconnects. The result is a 10 percent jump in chip performance, 20 percent reduction in power consumption and 30 percent more chips per wafer, due to the smaller size, according to the company.

    I wonder if anyone has looked into using fiber wires instead of copper in a PC. We all know fiber carries more data over networking lines, but I wonder how it would carry on sending light strands of electrical currency from chips to wherever.

    I'm sure someone has probably attempted this, but to date I've seen nothing on it, maybe someone would care to share a link or something.
  • Actually this could be an improvement above and beyond what is perdicted by Moores law.

    Moores law comes more into effect because of the improvements in the processes. 1 year ago we were developing in .25, now we are developing in .12.

    This added improvement will go above and beyond this. And is actually quite impressive.

    I look forward to hearing more about this, and possibly testing out this new tool.
  • Actually the price would be the same. The only cost would be the cost of the development tools.

    I am currently using the Avanti development tools, and they are already outragiously priced.

    So most likely the chip would either stay about the same price, or maybe even cheaper depening on the cost of the tool itself...the actual development of the chips would be the same price since it's the same process.
  • Actually this technology offers all sorts of advantages. In the realm of heating, since there will be less interconnects, that means less resistance, which in turn means less heat being generated. The number of transistors will still be limited by the process that they are developed in. Only the congestion of the interconnects will be lowered.
  • The REAL issue here is whether or not this will make microchips attractive any more. The main reason I support the use of microchips (over, say, vacuum tubes) is that they look real pretty when you blow up their pictures into poster size. The reason they're pretty, tho, is because there aren't any diagonal lines. Will chip designers keep aesthetics in mind with this new drawing tool at their fingertips? I think not. Support right angles! Support attractive computer chips!

  • Crosstalk? (Score:3)

    by Ted V ( 67691 ) on Tuesday June 05, 2001 @08:03AM (#175095) Homepage
    Isn't it significantly harder to catch issues like crosstalk between wires when you can run in 4 different directions? In my experience, the biggest issues in semiconductor design are finding tools that detect and solve the design problems, not actually using the new fabrication technologies.

  • I'm somewhat skeptical (Score:5)

    by taniwha ( 70410 ) on Tuesday June 05, 2001 @08:16AM (#175096) Homepage Journal
    Their press release claims they comtinue with normal style routing on M1-M3 (so people can continue to use their existing cell libraries - this means that the raw gates will NOT run any faster - gate layout is usually done in M1 and a bit of M2 and the silicon below). What they are proposing is a better long wire routing (it seems they rotate the M4/M5 grid by 45 degrees - and that's what those upper layers are usually used for) which is a good thing since wire loads are what's currently killing us in timing - theorretically (best case) you can get a sqrt(2) drop in R and another in C (for a product of 2x speed up in wire delays) when you replace 2 wires with their diagonal - not all wires are going to be perfect 45 degree replacements. Also I suspect there's asome problems with getting the 2 grids to line up - I bet there are limitations on where vias can poke thru.

    What I am skeptical about is that it means a whole new routing infrastructure - not just new routing tools (which I guess is what they are really selling) but also 3d extraction tools, timing infrastructure, DRC etc etc getting all of this working from all the different vendors and getting it to work together is NOT going to be easy

  • Copper interconnects only got a 10 to 15% (maybe 20 in some special cases) performance improvement, so yeah -- it's the same thing.
  • Copper interconnects, and SOI came from IBM if I'm not mistaken. Just seems they've been doing a substantial amout of research in this area (if the above is true), and this seemed like a very obvious issue -- even if the solution wasn't.
  • Curious... I figured that IBM would be the one to finally get this kind of thing out the door. That said, they forgot to mention that two 45 degree angles creates less resistance to your confused electron than a single 90 degree angle -- shorter distance too which is a bonus :)
  • He would use neurons, and grey stuff (and curves, too).
  • Diagonal routing has been used to some effect on PC boards for a long time, but it's been hard to find enough wires going between the same sources and destinations to get a big group (river) together, so on a given layer they tend to cut off the vertical or horizontal routes that other pairs need. If you can arrange related groups of circuits to be adjacent ro on the same vertical or horizontal axis then diagonal routing isn't needed. It can certainly help time-critical signals in a sort of kludgey way if they're going to be wasting most of M4/M5 anyhow.
  • There's an obvious problem with using electronic cpu-cores and optic interconnects.
    You'd have to put a "electric to light" converter in one end of the fiber and a "light to electric" in the other.
    Those converters would take up lots of space inside the chips, generate lots of heat and connecting the chips would be a major hassle.
    You'd also have to use one fiber for each direction, doubleing the amount of interconnects.

    One solution, and I know people are working on this, is to build optic cpu's.
    Haven't got any links though. :-/
    A little now and then, news about optical logic chips float around but I've haven't heard anything in a while now.

  • And they would bend *in the wrong direction*, taking a turn through the powersupply before going to the destination.
    And instead of not sending electrons down a wire to represent a zero, he would us *a second cpu*, connected with another wire going to the same place. This would send a serie of signals indicating that "that one there is actually a zero now". ;-)
    (That is, if he design chips the way he design biological systems, like humans for an example.)

  • Okay. They have new design tools. Wonderful. Who's going to produce them? These days, mask data handlers deal with x,y coordinates and the Manahattan lines between them-- always assuming right angles. Diagonals are made by making very very small rectangles to approximate diagonal lines. So, what they're doing can be done, and is in fact done on the lower levels by macro designers. The problems with these in manufacturing are many. Not the least of which is the fact that all those tiny diagonals add up and create a huge data volume. An 18mm chip can require the best and fastest many-processor RISC server today. Surely the data volume will go up orders of magnitude using this process. Either the data handling methods of the facilities themselves also need to be upgraded, or this practice will be relegated to only the smallest of chips.
  • Did you read the article? It said that the lower metal layers will stay the same whilst the upper (eg. 4th & 5th) will run diagonally.
    --
  • 55% higher price
    43% more heat
    142% more FUD
    19% more Jon Katz (NOOOO!!!!)

    and finally...

    29% more made us statistics
  • Umm... Notice that they said "Metal 4" and "Metal 5". That means if you want to use a 45 degree interconnect, you via up to the diagonal layers. It isn't on the same layer as the other wires so it doesn't cut across them.

    I'm surprised it took this long for someone to get this done. I remember designers where I worked spending long hours trying to reroute cells to reduce parasitics on long wires.

  • Moore's Law doesn't just happen- it requires lots of improvements like this for it to be met. One can't just "sit back"
    and wait for it to magically make chips smaller, faster and cheaper; it takes human effort of this sort.

  • Just an Interconnection change... (Score:4)

    by Orne ( 144925 ) on Tuesday June 05, 2001 @10:45AM (#175109) Homepage
    When I first saw the title, I saw "diagonal" chips, and in my mind, I imagined layers of silicon wafers stacked in 3D like //// with interconnections between layers running \\\\.

    But no, all they did was decide that instead of the time-tested grid format, we'll just run our interconnection wires 45 degrees diagonally accross the chip, but still pretend there are grid "nodes" for automation purposes. (for those not in the know, interconnect are the higher-level wiring that connects "blocks" of circuits together, such as connecting adders to multiplexers)

    Building 3D layered chips is a whole 'nother beast.

    Just remember, they're only saving wiring only at corner-type junctions, and even then, only what can be optimized to fit within the existing wiring mesh. Still, saving wiring is a big improvement; as we should all know, excess wiring causes heat, voltage, and frequency problems (due to line charging effects). On the other hand, most modern toolkits are written to optimize to a 2-D grid, not to mention most modern lithograph manufacturing tools. But, thats the point of the "discovery".

    -- Scott
    ... who should be working

  • Well, it depends. Less power means less heat, but if the advance also means higher density is possible, then your power-per-circuit drops, but your power-per-surface-area could potentially increase or break even (because you're using lower power per circuit, but more circuits).

    --S

  • Re:10% is a breakthrough? (Score:3)

    by mccrohan ( 147132 ) on Tuesday June 05, 2001 @07:46AM (#175111)
    Sure, it's obvious that connecting on the diagonal will save you distance. Duh. However, no one has managed to do it reliably and successfully until now. So, clearly, there's more going on here than 'basic geometry'. The article doesn't go into any real detail about what the challenges were and how they were overcome, unfortunately, so those of us who know nothing about chip design will have to wait for more info. --S
  • Forgive me for being an ignorant putz, but isn't the diagonal merely a perspective issue? I know I've seen cards with diagonals...this design doesn't carry over into IC's?

    A graphic, someone, PLEASE!
  • In multilayer PCBs the standard idea is to run most wires in one layer in the north-south direction and east-west in another, thereby minimizing distances (given a Manhattan architecture). With four layers you could be very effective using the diagonal directions as well, with the same principle; when almost all wires in a layer run in the same diagonal direction, you're not cutting off any "straight" wires.

    --

  • In short - no. Heat dissipation in wires is caused by internal resistance. Resistance in wires increases as length increases. If diagonal wires are used, wires can be of shorter length. This probably accounts for the 20% saving in power consumption.

  • immagine a beowolf...
    oh, never mind
    Allan
  • That was the point, yes.

    As far as your question goes, I'm certainly no expert on distributed processing. There are many very usefull sites on clusters and. If you're really interested, I'd start here:
    http://www.beowulf.org/
  • Why would IBM do this? They would be a company that would use this, not necessarily develop the tools to use it.

    IIRC, a 45 degree angle creates a slight bottleneck, increasing the resistance at the joint. However, the algorithm uses oblique wires for long routing, not lots of sharp turns (there aren't many of those, mainly between layers, and this won't affect vias).
  • Probably twice the big number per license (but I'm not sure).

  • Re:10% is a breakthrough? (Score:3)

    by hawkear ( 172947 ) on Tuesday June 05, 2001 @08:49AM (#175119) Homepage
    If you decided to read the article, you might have noticed that the example processes used 5 layers of metal. The first 3 were primarily orthogonal, so they would remain compatible with existing designs. The top two layers could be used for the diagonal interconnects.

    The breakthrough here isn't the physical ability to route diagonally, it's the algorithms used to handle routing diagonally (not an easy task).

  • ... and ... (Score:3)

    by boaworm ( 180781 ) <boaworm@gmail.com> on Tuesday June 05, 2001 @07:42AM (#175120) Homepage Journal
    > They're claiming 20% less 'wire', 10% faster, 20% less power and 30% better yields.

    ... and a 100 % higher price ? :)

  • Although there are many technical hurdles, the amount of wire in a 3D arrangement would be even less. Add high temp superconductors and we can sustain Moore's law for another 20 years.

  • IIRC, the article mentions that for most 90 degree angles, they have to put in a via, which tend to take up space, not only on the current layer, but on the layers above and below you. So, removing even 20% of the 90 degree angles should greatly reduce the floorspace used on a chip. (less space = smaller chip -> faster system) But, it's been a while since I dealt with CPU/digital design, so I could be mistaken.

  • What is "outrageous"? $50,000, a $100,000?
  • Don't they run into cooling issues if they have a method to cram more transistors/cells into a given volume ?

    I doubt it. "The result is a...20 percent reduction in power consumption," according to the article. Less power means less heat.

  • 10% is a breakthrough? (Score:4)

    by mblase ( 200735 ) on Tuesday June 05, 2001 @07:40AM (#175125)

    A perfectly obvious way to shorten wire lengths using basic geometry, resuling in a mere 10% improvement in performance, qualifies as "a semiconductor breakthrough as significant as copper interconnects"?

    According to Moore's Law, I could have gotten the same improvement simply by postponing my purchase for two months.

  • If they are going to minimize distances in two dimensions, it seems that a hexagonal architecture would be better, since six elements can be placed at a minimal distance as opposed to 4. In addition, if you offset the rows of hexagons correctly, you have sphere-packing architecture, where each element has 12 minimal-distance neighbors. For static chip architectures (ones that don't change in time), this should result in the shortest distance between computing elements. My guess is that a 3-D sphere packing architecture would be the best overall, but some smart scientist will probably come out with a 4-D sphere packing architecture that depends on 24 minimal distance time-variant elements. That might be the limit, at least until we start using superstring computing elements! (grin)

  • (another) God's chips (Score:3)

    by Quietust ( 205670 ) on Tuesday June 05, 2001 @08:44AM (#175127) Homepage
    "If you think about how God would design a chip, obviously God would use 45 angles"
    If you think about how God would design a chip, obviously God would use curves.

    -- Sig (120 chars) --
    Your friendly neighborhood mIRC scripter.
  • I don't think it was arrogant, just a reminder that working at right-angles reflects a limitation of Man's techniques, not a law of Nature. He didn't, for instance, suggest that God would use only forty-five degree angles, merely that He would use them, probably in conjunction with other angles, if He were designing a chip, perhaps as part of a guidance system for a more advanced version of the Holy Hand Grenade (the Holy Smart Bomb?)

    The real question, of course, is how many pins God's chip would have, and how many angles (dancing or otherwise) there would be for each pin. This issue may occupy the staff of Jesuit Research Technologies for some time to come.

  • yeah, it makes sense if you don't think about it. the actual cells of the eye are evolved to try to cope with the way that nerves lead out of the eye. to argue that these adaptations are a good reason for the way the nerves are is simply irrational; it's putting the cart before the horse.

    I'm by far not a creationist (I am an atheist!, but that is just so I can be an ist of some kind).. darwin all the way and stuff.. but when I read this the first thing I thought was that it sounds like some kind of hack from god's nerve department.. like they found a bug in using the nerves turned the correct direction, and when playing around found that bug was less common when turned backwards, so in order to make the shipping deadline (7 days to ship isn't much time!) they turned the nerves around and released.. for better or worse.. :).. rofl..
  • It seems remarkable to me that just because people
    cannot fathom the reason why something is designed
    in a counterintuitive fashion it means that either
    a god did it for some inscrutable reason or because
    it's inherently wrong.

    Steady there big guy.. I was doing this thing called 'making a joke'.. I wasn't questioning if there was a god (I don't believe in god) or if he was right or wrong (if I did believe in god I would probably have an opinion on this.. but atm since I don't believe in him, no opinion).. I have no opinion about the whole silly nerve ending's direction thing.. it matters not to me.. I just thought it was funny sounding.. like you know.. something a wisen old hacker would do in order to get a product out the door, regardless if there is rhyme or reason to it.. *shrug*.. see.. joke.. funny..laugh.. not serious.. got it?
  • IIRC Moore's law is a statement on the rate of progress in integration. It doesn't apply to the methods used to achieve that rate of progress. There have been a variety of technological improvements besides die shrinks over the years (CMOS, copper) that have contributed to the exponential growth of integration.

  • What about Cooling ? (Score:4)

    by Rosco P. Coltrane ( 209368 ) on Tuesday June 05, 2001 @07:41AM (#175132)
    Don't they run into cooling issues if they have a method to cram more transistors/cells into a given volume ?

    My understanding is that modern processors use diamond to conduct heat outside the processor core : did they also create an orthogonal diamond layer to conduct the heat out ?




  • /



    There, was that so hard?
  • MicroSoft will be filing suit for patent infringement of their X-Box by this "X Architecture."
  • If you think about how God would design a chip, obviously God would skip the silicon, copper, angles of any kind, binary computing and everything we consider a computer and just make a better one. Unless he felt like using angles or curves or squiggly lines. He's kind of hard to predict, all that "mysterious ways" business I suppose.

    That being said it was a spectacularly arrogant quote.
  • Diampnd shapes? I'm not sure how were going to inspect those chips, but it sure will ba a challange.

    Matthew LaBerge

    August Technology

    "Automated Inspection Solutions"

    www.augusttech.com

  • There are chips that use fiber optics in them to transfer data. Theyre called optoelectronics, companies like digital optics, motorola and nortel networks make them.

    Matthew LaBerge

  • The problem is that Cu interconnects and SOI needed actual research and experimentation to accomplish. This announcement is trivial compared to those. Also Toshiba and Simplex have nothing to do with the actual "technology" when it finally works (will take 2+ years). The goal is basically implementation of an e-beam etcher that can draw in arbitrary directions which will be done by companies like Applied Materials. There's nothing special about the software they'll be using.
  • It isn't too hard to figure out why they are referencing pythagoream theorem, is it? Previous routes were rectilinear, now routes can use the hypotenuse. The difference in route length (best case) can now be computed using the pythagoream theorem as a route of length 2 (one unit horizontal, one unit vertical) can be reduced to 1.41.

    So if every single route used straight lines, the routes would be MAXIMUM of 30% shorter. That's if every single layer could use perfectly straight connections between routing points going at arbitrary angles (actually for 30% that means every route goes at 45 degrees which is stupid because then why don't you just rotating the whole chip by 45 degrees!).

    The best case unfortunately is not going to happen. With five routing layers and route length uniformly distributed, if you decrease the route length on layers 4 and 5 by 30% you only get overall a 12% decrease in wire length. And that 30% is a theoretical best case! On real designs if you restrict layers to only use 45 degree angles, you will never get even close to the maximum of 30%.
  • I tried to diagram this, but Slashdot said that I was lame.

    If each pair of legs of a right triangle on the original chip were replaced with a hypotenuse on the new chip, this would indeed result in using less wire.

    It is true that this algorithm would result in a design that's isomorphic to one that COULD be made with -| layout, but it's not strictly the same as the one obtained by rotating the original chip 45 degrees.
  • This was of course assuming that the original chip had a wretched design, and used two perpendicular wires for every connection.
  • "Dubbed the X Initiative, this consortium ..."

    So are they going to call themselves The X Consortium? ;-)

    Also, if they make this a free standard (as in free software), maybe we'll see the XFree86 line of x86 (X86? Xx86?) compatible chips.

    Not to mention the X architecture of future graphics chips being called 'the basis for windowing user interfaces'.

    --

  • "If you think about how God would design a chip, obviously God would use 45 angles," said Kurt Keutzer, professor of electrical engineering and computer science at the University of California at Berkeley.

    Yeah, but this is the same God who designed our lousy eyeballs with the nerves on the inside, giving us a blind spot. And what about teeth? What crazy design idea was that?

  • yeah, it makes sense if you don't think about it. the actual cells of the eye are evolved to try to cope with the way that nerves lead out of the eye. to argue that these adaptations are a good reason for the way the nerves are is simply irrational; it's putting the cart before the horse.

    c'mon these are people who actually believe that God created fossilized dinosaur remains to test our faith in creation.

  • Less power and better yields are a big deal, because those properties don't scale with Moore's Law - quite the opposite.

    And even though diagonal wiring might seem like an obvious idea, I bet developing good routing algorithms that can take advantage of it is not easy at all. Most of the interesting problems in circuit interconnection are NP-complete.

  • "If you think about how God would design a chip, obviously God would use 45 angles..."

    If God built them they'd have brains you putz.....


    DocWatson
  • I think God would be more into quantum computing. I mean, I'm pretty sure God could figure it out - and maybe use something better than 0's and 1's, and give it a more origonal name instead of something with an 'X' in it.
  • I may be ignorant but after reading the two articles it seems to me that there is no real breakthrough. It all boils down to new routing algorithms.

    I think that the basic problem has been that single-layer routing algorithms have a decent time complexity (O(N^2) I think), while multi-layer routing algorithms have exponetional time complexity (O(N^N) as I recall), so it has not been feasiable to use general routing algorithms for the multilayer problem with millions of connection points unless you restricted the problem to "Manhatten" layout.

    There is some minor technical problem (lasers going diagonal in addition to up-down+left-right), but what is the big deal?

    What am I missing? Or is it really all hype?
  • ... and a 100 % higher price ? :)

    Maybe at first, but don't higher yields usually lead to cheaper prices?
  • it seems every thread i read on /. has a post about "imagine a beowolf cluster with (insert article subject here)" i guess it just must be stupid joke like "all your base are belong to us"...man that really died fast eh? good post neo_phyter....make fun of all those people posting about beowolf clusters btw what is a beowolf cluster? :D

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