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Intel Technology

Strained Silicon Chips From Intel 126

Quirk writes "NewScientist is reporting... "Intel has taken the wraps off a secret technique it is using'Strained silicon' chips to increase the speed of its Pentium and Centrino chips. The technique boosts the rate at which transistors switch, without having to make them smaller.""
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Strained Silicon Chips From Intel

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  • by RalphBNumbers ( 655475 ) on Tuesday December 23, 2003 @09:08PM (#7799778)
    I know IBM has been publically working with this, at least in research, for a long time, and it's a fair bet other firms were too.
    IIRC they've even used SSoI (Strained Silicon on Insulator) for some production ASICs...
    • by Dreadlord ( 671979 ) on Tuesday December 23, 2003 @09:13PM (#7799802) Journal
      true, I was going to post something similar, here is the link to IBM's research about Strained Silicon. []
      I first thought it was the submitter's mistake, but actually the story is taked off the article.
      Maybe someone can shed some light here.
      • by metlin ( 258108 ) on Wednesday December 24, 2003 @02:30AM (#7801219) Journal
        During my undergrad, one of my professors of Solid State Circuits lab talked about this. She said that the reason this is hard is because when your source/gate region is partially depleted of charge carriers, there is a need to raise the source-drain gates effectively to utilize the technology. You see, one of the benefits is that the effective capacitance of your source-drain region is decreased. However, if your source-drain gates are not sufficiently increased, the remaining charge carriers remain back and over a period of time this in itself builds up a capacitance. It then begins to function like a dual capacitor device, etc.

        And to counter this, you will end up using metal within your S-D zone, however that will have its own side effects - you will need more interconnects and this will increase the resistance by a very slight amount. Trivial for a small number of transistors but if you're having a few million of them, it could be painful. Also, it would mean that the entire thing is going to heat up ever so quickly.

        And ofcourse, you always have issues with the Floating Body effects [] (warning Powerpoint).

        Couple this with a hard manufacturing process, and you have a technology thats atleast going to take another 5-10 years to mature. And thats being optimistic :)
      • There is a difference between understanding and using. Intel has announced that they are using strained silicon in a production environment. The big difference here is scaling the process up. As they mentioned in the article, they have disclosed their use of, but not how their strained silicon electronics are made.
      • The secret is that Intel figured out how to do it... CHEAP.
    • by cmacb ( 547347 ) on Tuesday December 23, 2003 @09:16PM (#7799819) Homepage Journal
      I bet what the article MEANT to say was that they took the wraps off the fact that they are using this process. The secret being not the process but their use of it. Especially since they credit a university researcher with the concept back in 1992.
    • Look Here [] for Strained Silicon Secret.
    • The secret apparently is the production process used to utilize the strained silicon technology. It's one thing to have the theory and quite another to have it working on a large scale. And Intel is making use of both compressing and stretching the silicon, something that really enhances performance.

    • Since when is Strained Silicon Secret?

      The idea of strained silicon is to apply a mechanical stress to the silicon. This will change the spacing between the silicon atoms (the lattice spacing), which will indirectly reduce the channel resistance, therefore allowing faster transistor switching speed.

      Indeed, this has been known for a long time, but so far it has not been used in commercial products due to the problems involved with the actual manufacturing of theses devices.

      The classical way to manufacture
    • I attended a lecture on this topic several years ago. One of our professors used silicon straining to alter the wavelength of LEDs. He had originally noticed how the wavelengths of LEDs of different materials correlates with the interatomic separation in the material. That led him to think whether it's merely the lattice separation, instead of the material itself, that matters.
      • "That led him to think whether it's merely the lattice separation, instead of the material itself, that matters."

        I cant help but commenting here: This is a trivial result of even the simplest models to explain the existence of a band structure. (tight binding, kronig-penny etc) I guess he did not just realise it experimentally.
  • by Anonymous Coward
    Dupe, Maybe read this []2.5 year old story
  • by BWJones ( 18351 ) on Tuesday December 23, 2003 @09:15PM (#7799813) Homepage Journal
    Shoot, I should tell you about strained silicon. That overclocking experiment I did a couple years ago went horribly wrong when the water pump failed and smoke started pouring out of the case. THAT was decidedly strained silicon. :-)

  • by Craig Maloney ( 1104 ) * on Tuesday December 23, 2003 @09:16PM (#7799818) Homepage
    Intel sees chip futures strained
    Intel strains to find new chips
    Intel strains to make chips faster

    etc... ad nauseum.
  • Hmm.... (Score:3, Funny)

    by Anonymous Coward on Tuesday December 23, 2003 @09:17PM (#7799822)
    Pulling on my processor with two pairs of pliers just bent a few of the pins and made it smoke a bit...
  • Mechanical Stress (Score:5, Interesting)

    by miracle69 ( 34841 ) on Tuesday December 23, 2003 @09:17PM (#7799825)
    All of this is at the atomic level, but I do wonder how these things hold up to mechanical and thermal stress.

    To stretch the silicon lattice, Intel deposits a film of silicon nitride over the whole transistor at high temperature. Because silicon nitride contracts less than silicon as it cools, it locks the silicon lattice beneath it in place with a wider spacing than it would normally adopt. This improves electron conduction by 10 per cent.

    What temperature ranges does this become an issue? If my processor gets warm, will its performance decrease because the strain dissapeared?

    Would mild mechanical stress on the chip (i.e. application of heat-sink) alter the strain?

    • I'd like to know if the lattice could be stretched in all three directions, rather than just one. And if so, would that provide any benefit? Or does the benefit come from that directionality?
      • Re:Direction (Score:3, Informative)

        I'd like to know if the lattice could be stretched in all three directions, rather than just one.

        Based on the quote in the grandparent post (and the picture at the bottom of the page in the article [], which shows a side-slice of the configuration), the strain is 2D already (plane face to plane face).
        The only way to get 3D straining would be to have a 3D substrate, with the transistor material embedded within.
        It seems to me that, in such a configuration, the substrate would interfere with the operation of th

      • Re:Direction (Score:2, Informative)

        by n7ytd ( 230708 )
        I'd like to know if the lattice could be stretched in all three directions, rather than just one. And if so, would that provide any benefit? Or does the benefit come from that directionality?

        It would be stretched in all directions, but usually the thickness is kept as small as possible, so the effect in that direction is minimal. The idea is to increase the carrier mobility between the source and drain, which is mostly a 1-D proposition: the electrons (or holes) flow from the source towards the drain,
    • Won't happen (Score:3, Insightful)

      Anything P4 and later has the built in temp sensor that slows down the cpu if it overheats. If your cpu is getting so hot that its melting silicon then you have bigger problems to deal with. The tomshardware video still gives me a chuckle when the AMD chip goes *poof* and smokes without a heatsink. Trying to save a few cents I suppose.

      • --BTW, Tom's Hardware worked / is working with AMD to prevent these catastrophic failures from happening in the future. I think the chips made after that article started incorporating safety features.
    • Re:Mechanical Stress (Score:5, Informative)

      by mercuryresearch ( 680293 ) on Tuesday December 23, 2003 @10:46PM (#7800378) Journal
      I spoke with Intel about this in the spring.

      Apparently the strained silicon technology came about due to research related to mechanical stress problems they were encountering across the entire chip -- so it already was an issue. Their research solved the mechanical stress problem, and they later realized by intentionally localizing the effect they could basically place the strain at individual transistors to improve performance.

      Because the effect is localized and controlled it's no longer an issue of concern, AFAIK.

      Heat sinks, etc, shouldn't alter the strain at the transistor level. Remember, we are talking about this at the atomic level, so any macro-level strain like a heat sink would have to be pretty substantial to work its way down into the crystal lattice structure to the point of affecting performance. (Sort of humorous if it did, though, as it would imply microprocessors would go faster if you squeezed them. In reality Intel is actually stretching the size of the normal silicon lattice structure, so heat sink stress (compression) would actually be working against you, but it's also occuring in the wrong axis (the lattice stretching is 2D X-Y, not Z-axis.)
  • by Amiga Lover ( 708890 ) on Tuesday December 23, 2003 @09:21PM (#7799841)
    ...who claim we're coming to the limits of silicon, and XXXX MHz is the highest that can be achieved. Technology will keep on advancing relentlessly, changing and adapting.

    Pick an absolute limit for the speed of a CPU... then proceed to completely ignore it. Can't go wrong there.
    • we are coming to the ends. for Intel, they need to reduce the leakage or they will not be able to compete.
    • If I'm not mistaken whan't it Intel themselves that said that the theoretical limit was fast approaching?
    • by Waffle Iron ( 339739 ) on Wednesday December 24, 2003 @02:38AM (#7801257)
      ..who claim we're coming to the limits of silicon, and XXXX MHz is the highest that can be achieved. Technology will keep on advancing relentlessly, changing and adapting.

      While technology could keep advancing for quite some time, that doesn't mean that advances will be economically feasible.

      Take aircraft development, for example. The maximum speed advanced on a roughly exponential scale from 1903 through the mid 60s, culminating with an X-15 flight at around mach 6. Even today, researchers are tinkering around with models of aircraft faster than that. However, 99.99% of all passengers and cargo still move at the speed they did in 1960: about 500 mph. Why is this? Because fuel consumption and noise problems make it uneconomical to go faster than a 707. For air travel, every day reality has become decoupled from technological possiblity.

      Likewise, CPU performance will almost certainly hit a wall where the power consumption makes it impractical for the average user to run more MIPS. Processor technology will continue to advance, but only for applications where power consumption is no object.

      The problem is that when you can no longer target CPUs at the mass market, the potential revenue shrinks, so investment money dries up, slowing the development cycle. (This is a big part of the reason why 40 years after the X-15 and SR-71 we haven't come up with anything faster.) This will be the factor that ends exponential silicon CPU performance increases, even if there is no fundamental physical roadblock to producing faster processors.

      • Or we'll get to the point where our processors contain cells, and each cell can be doled out "work units" to handle. Mass a bunch and you can complete more "work units" faster. Each "work unit" would probably be a thread, so that data could be collaborated easily. Maybe our programming models in the future wil be so totally different that processor design as we know it will be like looking at the horse and buggy today.
        • Maybe our programming models in the future wil be so totally different that processor design as we know it will be like looking at the horse and buggy today.

          They said the same thing in the 60's and 70's, after Algol (procedural language) and Simula 67 (OO language). Yet, somehow, 30 years later we're still programming with the same concepts as in 1967!
          The truth is, new ideas may come, but people don't change that quickly, and we won't be able to change the way we think very quickly either.

        • That is already on the books at Sun. Take a look at Sun processors. [] Sun is pointing toward massive threading as the future. Now, I work for Sun and could very well be within the "bullshit field" and not know the truth from a M$ press kit; but it is an interesting direction for server CPUs. It would not help desktop apps though. I recall Carmack's QuakeIII discussion of how difficult it was to wring any performance benefits from dual cpus. I doubt having 16 threads will be of any benefit to Quake5 or
      • Perhaps the speed barrier has already been reached in the processor world. There is an Israeli company called Enlight that has recently released a new type of processor that makes strained silicon look obsolete and decrepit. Too bad Intel, Enlight is years ahead of you.
  • The announcement, at the International Electron Devices Meeting in Washington DC last week, gives a glimpse into the intensely secretive way chip firms attempt to gain an edge over their competitors in a market worth over $100 billion a year. Chip market worth 100 billion dollars ? Wow. That is the thing that stood out for me in the article.
  • by MBraynard ( 653724 ) on Tuesday December 23, 2003 @09:26PM (#7799870) Journal
    Man made diamonds have much less problems handling heat and Intel is ignoring this while their competitors are on the fast track.

    Still, Butler is frustrated with what he thinks of as myopia in the US computer business. "Europe and Japan have been investing in diamond semiconductor research," he says, citing the Japanese government's announcement in December that it would begin allocating $6 million a year to build a first-generation diamond chip. "Bob Linares has given the US the advantage, but nobody's paying any attention," he says. "If we're not careful, the Japanese or the Europeans are going to claim the diamond niche."

    Indeed, Intel's top materials executives weren't aware of the latest research breakthroughs when I spoke to them in June, although they certainly understood the potential for diamonds in computing. "Diamonds represent a seismic change in semiconductors," says Krishnamurthy Soumyanath, Intel's director of communications circuits research. "It takes us about 10 years to evaluate a new material. We have a lot of investment in silicon. We're not about to abandon that."

    Click here for full article. []

    • Intel may be right (Score:2, Interesting)

      by dus ( 139697 )

      Intel may be right on this one - they always have been conservative and this worked out very well for them. Large companies often wait for smaller companies to take the risk and prove or disprove the viablity of new tech. Nobody knows how well diamond is going to work out!

      Remember GaAs?
    • by DAldredge ( 2353 ) <SlashdotEmail@GMail.Com> on Tuesday December 23, 2003 @10:36PM (#7800322) Journal
      It costs around 1.5 - 2.75 BILLION USD for a new chip fab. Intel isn't about to throw that away, they will just buy one of the smaller companies when/if the perfect this tech.
    • In my New Employment Orientation (NEO) at Intel, they basically said ~The only way we'll ever get beat is by some minor startup nipping at our heel~. The jist of it is they said they will not get bogged down in old ways of doing things and will constantly change. Well I think the CEO needs to take NEO...
    • Man made diamonds have much less problems handling heat and Intel is ignoring this while their competitors are on the fast track
      I'd wager they aren't ignoring it at all. Rather, Intel will be keeping any progress on such a jump in technology very, very closely guarded to their chest.
      • I think Intel is secretly working on using diamond material in circuit design which may make possible a quantum leap in speeds for the CPU. Can you say 50 GHz clock speed for a CPU within six years? :-)
        • Yeah, thats great and all......but something has to change in the interface and imput dept. for that to mean anything at all. I think the usefullness of our methods of getting input into a computer ( think keyboard, think mouse ) are incredibly behind the times. Who is going to lead the music input and speech input wars? Thats what I wanna know. it's about time computer makers started worrying less about how many Ghz they can wring out and start bringing us some actual advancements in technology that MEAN
  • by JanneM ( 7445 ) on Tuesday December 23, 2003 @09:55PM (#7800097) Homepage
    In a response, AMD announced development of "stressed silicon", while VIA reportedly has only managed to "get their silicon slightly worried", according to one unnamed source. China, meanwhile, announced a multi-million dollar project to have silicon going into hysterics within five years.

  • by vudu ( 223094 ) on Tuesday December 23, 2003 @10:00PM (#7800131)
    Silicone? I was expecting a story about Pamela Anderson.

  • PFET vs NFET (Score:3, Informative)

    by ChrisMaple ( 607946 ) on Tuesday December 23, 2003 @10:41PM (#7800353)
    Note that Intel improved the P channel devices 25% and the N channel devices 10%. Since N channel devices are usually 2 to 3 times stronger than P channel devices, this reduces the difference and makes CMOS design a little bit nicer.
  • news (Score:3, Interesting)

    by ruiner5000 ( 241452 ) on Tuesday December 23, 2003 @10:54PM (#7800413) Homepage
    Headline-Intel sees IBM and AMD tech doing well, decides to copy.

    link []

    Silicon on Insulator, Copper Interconnects, DDR memory, dual core, but not HyperTransport yet.
    • Hehe, AMD. Yeah, look at all the money they're raking in - there's something to copy.

      You also seem to be under the incorrect assumption that IBM or AMD "invented" any of those things. This is _truly_ funny considering AMD has (barely) eeked an existence out of basically COPYING/LICENSING OTHER PEOPLES' TECHNOLOGY. This is sure innovative, eh?
      • You seem to be under the incorrection assumption that I or anyone values your opinion not based on FAQs. We don't. Do some research then come back and post again when you are ready. And everyone other x86 clone didn't do that? So AMD copied x86-64, HyperTransport, 3DNow!, and copied Intel by working closely with memory, chipset, and motherboard makers? They copied them by not forcing standards down their throats? Hello, Rambus, and a new socket every quarter, and the blessed ia64. Show me where AMD ha
        • Oh come on, you're joking right? AMD does not make money. End of story. Their stock price is irrelevent.

  • "Intel has taken the wraps off a secret technique it is using..."

    Strained Silicon: Ancient Chinese Secret....


  • by DumbSwede ( 521261 ) <> on Wednesday December 24, 2003 @12:46AM (#7800903) Homepage Journal
    Sure strained silicon is great, but the real advance was the world's smallest colander.
    • Sure strained silicon is great, but the real advance was the world's smallest colander.

      I am *so* glad I wasn't the only one who thought of that sort of "straining". I read the article and *still* had to take a beating with a cluestick before I figured out that they were talking about the other meaning of "strain". I guess I was thinking about upcoming Christmas dinner.

      On a side note, I figured infinitesimal colander [] would be close to a Googlewhack [], but instead it brought up yet another bizarre collecti
  • by NerveGas ( 168686 ) on Wednesday December 24, 2003 @01:29AM (#7801034)
    There are several new technologies that either are speeding up chips, or will speed up chips, and the best part is that they'll all work together.

    For some time, SOI (silicon-on-insulator) has been helping chip manufacturers squeeze out extra performance. And the straining of the silicon lattice (strained silicon) helps as well. And you can combine them into SSOI, strained-silicon-on-insulator.

    Well, there's also one other technology that's been developed, called "fully depleted silicon". And guess what - it should/will be possible to make fully-depleted, strained silicon-on-insulator chips. (FDSSOI?)

    Between moving to 90 nm, then 65nm, and then further, as well as integrating high-K dialectrics and fully-depleted, strained silicon-on-insulator manufacturing technologies, we've still got a lot of headroom to keep cranking out faster and faster processors. Moore's law has still got a long time to live. And that's even if we don't make any new breakthroughs, but my guess is that the chip makers will continue to pull aces out of their sleeves, so to speak.

  • The article states that compressing p-doped regions improves hole conduction and stretching n-doped regions improves electron conduction. Fair enough, but to me the p-doped and n-doped designations are either backwards or irrelevant.

    For example, an n-channel MOS device is built in a p-type well. The channel (region between source and drain) is p-type when the device isn't conducting current, but the channel must be inverted to n-type before electrons can flow from source to drain. Correct me if I'm wr

I've noticed several design suggestions in your code.