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Researchers Create 3-Dimensional Chips 243

Posted by timothy from the hypercubic dept.
Spy der Mann writes "Professor James Lu and other researchers of the Rensselaer Polytechnic Institute, managed to create three-dimensional chips (coral cache) to optimize the design of future processors and prevent overheating. "Make the interconnect wire shorter, and you cut the delay time," says Lu. "A simple way to make them shorter is to stack the transistors.""
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Researchers Create 3-Dimensional Chips More

Researchers Create 3-Dimensional Chips

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  • Heat (Score:4, Insightful)

    by skraps ( 650379 ) on Monday July 18, 2005 @07:51PM (#13099769)
    Hopefully there will be a parallel advance in cooling technology.

    • shorter wires = less resistance (Score:5, Informative)

      by SuperBanana ( 662181 ) on Monday July 18, 2005 @08:23PM (#13099976)
      Hopefully there will be a parallel advance in cooling technology.

      There is, sort of. If the wires are shorter, they have less resistance end-to-end assuming they have the same thickness, are made from the same material, etc etc. Less resistance means less heat (and maybe core voltage could be lowered slightly too, since there would be less of a voltage drop). However, I honestly don't know how much heat comes from the actual junctions versus circuit pathways.

      • Re:shorter wires = less resistance (Score:5, Insightful)

        by jumpingfred ( 244629 ) on Monday July 18, 2005 @08:37PM (#13100059)
        Most of the heat is disapated accross the transisors. Shorter wires may reduce the capacitance which would lower the amount of charge moving which would lower power.

      • Re:shorter wires = less resistance (Score:5, Insightful)

        by geekee ( 591277 ) on Monday July 18, 2005 @08:41PM (#13100084)
        "There is, sort of. If the wires are shorter, they have less resistance end-to-end assuming they have the same thickness, are made from the same material, etc etc. Less resistance means less heat (and maybe core voltage could be lowered slightly too, since there would be less of a voltage drop). However, I honestly don't know how much heat comes from the actual junctions versus circuit pathways."

        I don't think people are worried about the heat dissipated in the actual wire. High resistance wires require you to use additional buffers to generate signals with acceptable rise/fall times due to rc charging effects. This costs more power.
      • I have to correct you. Since I = V/R where I is the current in amperes, V is the voltage, and R is the resistance in ohms, less resistance means more current. Current is what creates heat and gets work done. Resistance isn't friction, it's simply the volume of electron flow possible through any given medium. Your observation that there would be more resistance was correct, however it would result in more heat. Take basic high school physics before youn try to work that out again. I would know - we did
        • At least not in the USA.

          I always thought it was the resistance that caused heat and not the current.
          Anybody got any links that demonstrate what the correct situation is?

          ...and I want a good explanation, not one that just says it is so.

          • Re:Sorry that isn't covered in High School Physics (Score:5, Informative)

            by ColaMan ( 37550 ) on Monday July 18, 2005 @09:56PM (#13100474) Journal
            It's all interrelated.

            The basic Power equation (in Watts) is Volts times Amps (V*I) .

            Aha! But from Ohms law, Volts is Amps times Resistance (V=I*R). And Amps is Voltage over resistance (I=V/R).

            So substituting back into the original equation ,Power can also be defined as :

            P = (I*R)*I = I^2R
            P = V*(V/R) = V^2R

            So you can hopefully see from all that mess, any change of voltage,current,resistance will change power dissipated.
            • "Power" is the measure of energy per time unit ( that is, P = E/t ).
              The heat dissipation is directly proportional (by a material-specific constant) with that energy (E), which is
              E = P*t = V*I*t = V^2*t/R
              As mentioned before, the heat dissipation wont' drop because the resistence is lower, but because that lower resistance allows a similar drop in voltage, and E depends on the square of V
            • for switching power (i.e. the dominant component) is C*V^2*F

              Where C is the capacitance (residual capacitance), V is the voltage and F the switching frequency.

              If you don't believe me, check some real research in this area, not your kindergarten texbook, like Wattch [harvard.edu]

              Shorter wires do make C a little bit smaller, but the dominant part there is the gate capacitance.

          • I always thought it was the resistance that caused heat and not the current. Anybody got any links that demonstrate what the correct situation is?

            (The following is extremely simplified, and ignores alternating voltages, capacitive and inductive effects).

            Two equations:

            U = I*R (Ohm's law)
            and
            E = U*I

            E is the heat energy
            U is the voltage
            I is the current

            Now, it depends on your situation. If your power source is constant voltage (or, in more engineering terms, it has low internal resistance, for exa
        • Or rather the experiment you pointed out is technically correct, but it does not fully model the situation. In fact, without any followup at all to that expermient describing more complicated circuits or at the very least, mentioning their existance, I would say that your high school cheated you.

          In your frankfurter experiment, The voltage was the same across each of the dogs and so the only thing that was different was the current as a result of the conductivity of the sausages. In this case, P = VI = V^
      • None of this is relevant in the long run. Eventually, chip manufacturers will hit the blank wall of the Heisenberg Uncertainty Principle. As you try to cram more transistors into smaller spaces (even in 3-D), you localize the electron wavefunctions (not to mention that cuttoff is achieved only if the electrons are in conduction bands, which will cease to exist if the transistors are too small). This means that they delocalise in Momentum space, and their Shannon entropy goes up, causing them to heat up dras
        • Heisenberg Uncertainty only matters if we're talking about modern physics. But what if we use post-modern physics, with a post-modern processor designed for post-modern programming? Will Perl be the language that breaks the Teradupes barrier? (One trillion dupes per year.) What then? Slashdot is only a few orders of magnitude away!!
        • I suggest taking a look at this paper [intel.com] which discusses theoretical limits on the binary switching model.
        • localize the electron wavefunctions [...] conduction bands [...] delocalise in Momentum space [...] Shannon entropy [...] entangled Greenberger-Horne-Zeilenger states
          Why not just reverse the polarity of the Heisenberg compensators and realign the plasma relays so that the main deflector dish emits a phased tachyon burst of Crayola radiation?
          Problem solved!
          • The next "revolution" (actually, evolution) will probably be in parallel processing.
            It's already starting, what with multi-CPU chips, multi-socket boards and all.
            (Actually, it's been going on for many years.)
            Eventually, each PC will have thousands or millions of CPUs, all working in parallel.
            The challenge is in how to get them to communicate efficiently with each other and with shared peripherals.
            Will the CPUs be configured as a hypergrid, as some sort of hierarchy, or something else?
            Will the CPUs be able t
      • Shorter wires do reduce the heat, but the wires are thinner, and most importantly the ratio of transistors to surface area (used to dissipate heat) has greatly increased. Even with the shorter interconnects, these 3-d stacked devices will generate alot of heat. This article [geek.com] from 2004 talks about this technology, and suggests:

        Moreover, stackable chips would exacerbate heat-dissipation issues since standard heatsink/fan combos probably can't cool an entire stack of chips. Semiconductor makers could choose
    • It will definitely be needed. With a traditional chip you have a lot of surface area for cooling. With a massive 3d chip you have a lot less outside surface area per transister. I think if 3d chips ever do come into existence they will have to be designed with 3d duct (or for water, pipe) work throughout to allow cooling.

  • 3-d (Score:2, Insightful)

    by PunkOfLinux ( 870955 )
    I think what they mean is that instead of the processor being on a single plane (a silicon wafer) it's on 2 or more wafers (stacked on top of each other or somesuch)
    • Blah blah blah...

      All I hear is that the new Mac cubes will be powered by Borg Cube Processors (copyright of Intel of course).

      If that day (n)ever comes, it would be great to see Steve Jobs with the Borg get-up too.

  • flavor ridges (Score:4, Funny)

    by cheesebikini ( 704119 ) * on Monday July 18, 2005 @07:53PM (#13099786)
    Flat chips suck. These chips have flavor ridges(tm).

  • Huh... (Score:4, Insightful)

    by Peale ( 9155 ) on Monday July 18, 2005 @07:53PM (#13099789) Homepage Journal
    I thought they'd been doing this all along.

    Guess I was just ahead of my time...in my head.

    • Re:Huh... (Score:3, Informative)

      by BayBlade ( 749886 )
      Well, thye haven't been doing it ALL along, but they've been doing it more more than a couple years already.

      P4's currently run on a 7 layer design and AMD 64's run between 4 and 9 layers depending on the specific model.

      I'm sure IBM does the same also.
      • Layer != Transistor layer. I think the layers you're refering to are just layers for the construction of a single transistor layer. I could be wrong though, so don't mod me up unless you're sure :)

  • Hey... (Score:5, Funny)

    by Anonymous Coward on Monday July 18, 2005 @07:55PM (#13099798)
    We complain about all the /. stories that are dupes but don't give proper credit to the editors when a non-dupe makes it past their radar. Propz to Timothy for posting an original article! Keep up the good work!

    • Re:Hey... (Score:3, Insightful)

      by ezberry ( 411384 )
      Technically you are congratulating him for doing what he is paid to do - no more. I mean, it's an interesting story, but I don't know if he deserves congratulations because he didn't chose to not green-light it.
      Maybe the parent was being facetious, but I can't tell.

  • Makes sense... (Score:4, Informative)

    by Bananatree3 ( 872975 ) on Monday July 18, 2005 @07:56PM (#13099808)
    It all depends on density of the transistors. You can squeeze 1 square mile into a 1 inch cube, but it will take 334,540,800 individual layers to do so.
    • Actually it would be 4,014,489,600 layers. :)
      (http://www.google.com/search?hl=en&q=square+inche s+in+one+square+mile [google.com])
    • And people wonder why the Imperial system should have died years ago.

      Wouldn't it be easy if non-trivial calculations like this were able to be done using powers of ten?
      • I dunno, frogbert, if units of measure intimidate you, maybe you should try this new thing we put together a few years back.

        It's called a calculator and it not only doesn't care what unit you prefer, it can change between them seamlessly and cleanly.

        Preference for units of measure have been irrelevant since the first portable calculator dropped (and even before that, if you passed math class.)

        Even reasonably modern calculators (like the wondrous and fabulous HP48 series [sourceforge.net]) have stone-awesome unit conv


        • I dunno, frogbert, if units of measure intimidate you, maybe you should try this new thing we put together a few years back. It's called a calculator ...

          Lockheed Martin agrees with you [space.com].
          • So - what you're trying to say is that if there were one system of units, this could have been avoided. Perhaps so. I rather think it's a lesson in not letting idiots onto a project, myself, but if it makes you go all Luddite, well, more power to you. How is that cave you live in, anyway - does the damp ever get to you?

            People make mistakes. That won't stop if you take their tools away from them, or leave them only with a hammer you happen to like. They'll simply find new ways to screw up, and if your "sol

            • It also happens a lot less often if you don't expect people to do unnecessary, difficult to trace work with useless repetitive tasks, such as doing unnecessary unit conversions. The use of calculators encourages this kind of idiocy, because when you say "1/4 inch" and get 0.65 millimeters out, you lose your sense of what the original unit was. [Note: it's actually 0.65 centimeters, not millimeters. You see the problem?]

              • It also happens a lot less often if you don't expect people to do unnecessary, difficult to trace work with useless repetitive tasks

                Computers. Programmable calculators. It's a revolution. Really. Put your abacus down and join the new age. You'll like it.

                Note: it's actually 0.65 centimeters, not millimeters. You see the problem?

                I certainly do. You shouldn't be allowed to do engineering work. The concept of validation has escaped you, not to mention your unit conversion problem. Thanks for c

    • ...except that a single silicon atom is .25 nanometers in diameter. So even assuming a stack of pure silicon, a 1 inch cube is limited to 101,600,000 layers, or roughly 0.025 square miles.

  • I'm Waiting for a 4-D Chip (Score:5, Funny)

    by DanielMarkham ( 765899 ) * on Monday July 18, 2005 @07:57PM (#13099813) Homepage
    Want to write a time travel game. Or maybe I already did.

  • 3d chips? (Score:5, Funny)

    by Anonymous Coward on Monday July 18, 2005 @07:58PM (#13099820)
    Already been done [illegaluturn.com].
  • Quick, someone send themselves back in time to blow this guy up.

  • Not just three dimensions (Score:5, Funny)

    by Anonymous Coward on Monday July 18, 2005 @08:01PM (#13099839)
    I read in a paper recently where scientists have had some success in developing a four-dimensional transistor by using nanotubes to set up a quantum Klein bottle wherein the current passes through Bohr space and thus runs parahybolically.

    In practice, you should actually be able to use this method to set up any n-dimensional transistor, provided you can find a sufficiently clean source of power. Modern power supplies have heretofore been plagued by an excess of static dissonance.
    • You can compensate for that static dissonace by rotating the power harmonics.

      -
    • If I were a marketer, I'd want to smack you right about now... ...Thank god I'm a tech :) Kudos!

  • How does that prevent overheating? (Score:5, Insightful)

    by Kjella ( 173770 ) on Monday July 18, 2005 @08:02PM (#13099850) Homepage
    Essentially, they say this packs it denser. And a cube vs a flat processor = less surface/transistor. I see only factors which makes this *harder* to cool. Maybe someone can explain...

    Kjella
    • "I see only factors which makes this *harder* to cool."

      Well ... this is a stab in the dark but with the shorter interconnects that come with this chip design, you'd likely get less heat generation. Or maybe they'll come up with a way to stick tiny heat sinks between the layers that draws the heat out of the chip. If they can come up with this kind of design, I'm sure they can come up with some sort of heat solution. :D
    • Wires will be shorter. Shorter wires give off less heat.
      I have no idea if that compensates for the decrease in surface area.
    • That's exactly what I was thinking. Maybe if they use slower transistors or decrease the density?
    • ...would be very helpful here. Excellent thermal conductivity would get the heat out of the centre. You'd still need some way to get it out of the package though.

      Perhaps the whole package should be made from diamond too.

    • They won't manufacture these things at such a level that they become a cube anytime soon. Each layer is very small (think the micrometer (1/1000 of a millimeter) scale or smaller), and based on the article they're talking about using 3 layers.

      The majority of the height of a typical chip is the external packaging, so adding 3 or even 50 layers is unlikely to result in a noticable increase in width, so heat sink design remains unchanged.

      Sure the heat would increase if you don't change the design, but no one
      • Your point is well taken except there are few technological issues:

        Yield: When you stack 4 layers up, the only economical way would be to test the four layers separately before stacking. Testing means that you would need pull the signals out before you can do that. You will lose some of the wirelength reduction advantage there because you will now have to design the system for intermediate testing. No, testing after all packaging is not a viable option. Do a simple calculation, if probability of one layer

        • While having more surface area for larger caches or what ever is a wonderful thing, where this stacking concept can really help out is helping with clock sync issues.

          Now that we're pushing into the GHz speeds on chips it is getting rather difficult to keep the whole chip in sync across the distances that the signal has to travel. By stacking the various segments of the chip you've eliminated another obstical for higher clockspeeds.
    • Perhaps, long extremely thin wires running everywhere have a very high resistance? (As I'm sure everyone knows, thinner wires have higher resistance than thicker wires of otherwise similar characteristics) Make the interconnects shorter and there is less resistance, less power used, and less heat to disperse. Still, cooling a sheet of something is harder than cooling a block of something.

  • Already been done. (Score:2, Funny)

    by Anonymous Coward
    Frito Lay developed the 3d chip a long time ago: Doritos 3D
    • The fact that anyone even bought one bag of Doritos 3D is absolutely hilarious. It was obviously designed to give chips of equivalent mass more volume to package less food in the same bag (I know, with all the air in a regular bag of chips it seems impossible, but they proved it isn't).
  • Oh good, so they figured out how to add the extra dimension into ICs now? I was tired of having my reality compressed onto a 2D plane everytime I wanted to use my computer.

  • Diamond heat sinks (Score:2, Interesting)

    by Anonymous Coward
    I remember there were tests using diamond deposited on chips as a strong heat conductor. The whole point was to help make multilayered chips possible. Haven't read anything lately but it sounded promising.
  • Been there, done that [taquitos.net].

  • See-through Super-Chips! (Score:4, Informative)

    by Savantissimo ( 893682 ) on Monday July 18, 2005 @08:22PM (#13099969) Journal
    This is really cool stuff. Essentially they're making silicon wafers smaller by removing all the silicon in the substrate after the wafer is fabbed. Then they can put this few-micron-thick layer onto another fabbed wafer - perhaps made with a different process - then they can repeat the process. This allows sensor, analog, processor and memory to be made in the best processes for each function but with communication channels tens of thousands of wires wide and only microns long.

    This article is worth reading - this is going to be huge. Also there is a really fantastic picture of a see-through microprocessor wafer with the article.

    From the article:

    Wafer-level stacking also allows for short connections between different types of chips. "Particularly today the industry is trying to combine memory with the processor, and more than half of the chip is taken up by memory," Lu explains. "When we stack layers, we have a processor on the bottom and layer the memory on top, with a short access time between them." Lu says the reduction of memory access time would be a huge advancement for large-scale computer clusters calculating nuclear reactions and weather broadcasting, for example.

    "You are also creating new functionality," says Nalamasu. "Such technology has vast implications, for example, integrating biochips with silicon chips. The wonderful thing is that if we adopt this technology, we'll develop things we can't even envision today."
    • In the short term, expect to see a lot of failed wafers. The alignment problems between different fabricated wafers are going to make the interconnectors mismatch and fail under stress, or as manufactured junctions "creep", especially under thermal load. Also expect to see some nasty behavior with capacitive or inductive coupling between transistors which are vertically on top of each other, instead of merely adjacent. Groundplane, groundbounce, and other related issues are about to take a quantum leap in c

  • Simple? (Score:4, Insightful)

    by Detritus ( 11846 ) on Monday July 18, 2005 @08:24PM (#13099981) Homepage
    "A simple way to make them shorter is to stack the transistors."

    There must be a new meaning of the word "simple" that I'm not familiar with.

  • Been done before, 23 years ago (Score:4, Interesting)

    by chiph ( 523845 ) on Monday July 18, 2005 @08:35PM (#13100048)
    IBM used a multi layer ceramic module with thermal conduction system on the water-cooled System 3090 mainframe, and still uses the technology today in their zSeries 990, known as the "T-Rex".

    The center layers of the substrate include 16 wiring planes arranged in x-y pairs to maximize wiring efficiency. Metallized, 0.12-mm-diameter vias on 0.5-mm centers are used for x-plane-to-y-plane connections. Voltage reference planes are appropriately interspersed for signal wiring impedance control.

    See: Thermal Conduction Module: A High-Performance Multilayer Ceramic Package [ibm.com]

    Chip H.

  • Hexahedral ICs (Score:5, Funny)

    by mbstone ( 457308 ) on Monday July 18, 2005 @08:39PM (#13100074)
    In other news, Intel engineers have developed a new dual-core motherboard featuring twin hexahedral processors and a new socket design.

    "We've gone beyond zero insertion force -- you just throw the cubes into the enclosure and they will connect," said an Intel spokesman.

    According to the spokesman, the functionality of the system will depend on the orientation of the chips as they land in their respective sockets. If the chips land on 7 or 11, Windows will run; 2, 3, or 12 produces the Blue Screen of Death. Similarly, any other number will produce an exception unless it is thrown again before a 7.

  • Time to break out the blue/red glasses!
    (ducks)
    Because it looked like a chip was coming right at me!

  • 3D chips (Score:3, Informative)

    by Wardini ( 608107 ) on Monday July 18, 2005 @08:57PM (#13100180)
    There are a lot of hurdles that this document doesn't really get into. It does mention manufacturing but here are some hard core items that need to be considered. 1. Yield goes as e^(-alpha * A) where A is your area and alpha is your yield coefficient. So if you have non-yielding chips on one wafer and you mate it to another wafer that also has non-yielding chips, your total yield goes down at somehting like Y^L where L is the number of layers and Y is the yield given above and Y is 1. So if your yield is 75% and you have 5 layers then your final yield will be only 23%. 2. Testing. If a whole wafer is bad and you put it in your stack of chips, all the chip stacks will be bad. It would be best to test before you put those wafers together. Thats not easy. 3. Packaging is a big issue. Will it be standard wire bonding or something else. Does this thing really generate a lot less heat? And are the interconnects really a lot shorter. If the chip to chip connects cost the same as inter die vias then maybe so but my guess is that those chip to chip connections are a lot more expensive and take a lot more area than vias within the same chip. And alignment of one wafer to the next is also an issue along with getting good interconnect all the way through those stacks. Anyway, those are some thoughts. Its clear to me that 3D chips are a long way off and have there place in very specialized applications in the near term due to the complexities mentioned above. Wardini
    • So basically, what you're saying are cons are actually pros. You just increased the granularity of the process. The total (unstacked) area of the chips will be relatively the same whether they're laid out flat or stacked, so the odds of the chip having no error in it are the same. However, whereas with current technology, the whole chip would have to be thrown out, in a stacked chip, only the bad layer would have to be remade. This assumes that it is possible to test layers separately. If it is possible, it
    • But assuming that they can test each layer independently before assembling them, there does come a BIG advantage: Since each layer is smaller (i.e. the chip is segmented) you can have more chips made per wafer. Since the number of impurities per wafer would likely stay the same, you'd have better yields. Today, one impurity on a processor scraps the whole CPU, whereas in a stacked design, an impurity in one of the execution units would only jeopardize the layer that unit is on.

      This also opens the door to d
    • What everyone seems to be missing is that the problems you mentoin are problems even with flat chips. The real problem with 3D is heat disapation, and the real advantage is faster switching times (smaller wires require smaller transistors with less capacitance that switch faster) and less clock skew. So this is probably best fit with microprocessors - clock skew is a killer, and you can always use speed. Of course, making it harder to cool doesn't help, but realistically we are nearing the limit of cooli

  • ALMOST not off-topic (Score:4, Informative)

    by Kagura ( 843695 ) on Monday July 18, 2005 @08:59PM (#13100189)
    I'd like to thank the author, Spy der Mann, for having the foresight to make a coral cache of the site before posting. Kudos to you, mate.

  • Gene Amdahl?? (Score:2, Informative)

    by seven of five ( 578993 )
    Didn't Gene Amdahl blow a fortune trying to do this 20+ years ago? I think the company was Trilogy. They did succeed in some die stacking technology but I think they ended up selling the ideas and it went nowhere.

  • fractal chip? (Score:3)

    by lawpoop ( 604919 ) on Monday July 18, 2005 @11:25PM (#13100903) Homepage Journal
    If we have a solid block chip, it's going to get very hot on the inside. Could they design some kind of fractal chip to create a reasonable trade-off between interconnection and surface space so that we could blow air over more of the chip?

  • Way too late, but... (Score:4, Interesting)

    by anzha ( 138288 ) on Tuesday July 19, 2005 @01:34AM (#13101401) Homepage Journal

    Seymour Cray with the Cray 3 [wikipedia.org] had his processor bricks made of Gallium arsenide. The wikipedia article has flaws (I'll try to fix later) but it has the point that he went down the route of the 3d chip and circuitry much earlier than this /. story.

    A brilliant man, Seymour...

  • Preposterous Scale Integration ... (Score:3, Interesting)

    by Ungrounded Lightning ( 62228 ) on Tuesday July 19, 2005 @03:01AM (#13101627) Journal
    PSI is almost upon us.

    FYI: PSI is a tale I spun in the '70s or so, when Large Scale Integration (LSI - eventually with a company named after it) and Very Large Scale Integration (VSLI) were industry buzzwords for ICs with a higher level of integration than a single-digit count of gates or flops to be externally interconnected.

    PSI would involve:
    - constructing a 3-D "chip"
    - using ion beam epitaxy and doping to build it up in layers
    - testing as you go using electron beams for power and signal injection and higher-voltage electron beams for "positive" voltage injection and as test prods (using secondary emission to pull more electrons than they insert and/or to read the voltage on the chip's internal nodes)
    - turning up the beam current to vaporize (and later rebuild correctly) any defective component so the whole thing ends up flawless despite its large gate count. (100% yield!)
    - using diamond for the semiconductor (mainly for its stability and heat conduction properties)
    - running it in an inert atmosphere (so it can get up to red-hot without burning up or converting into graphite)
    - building it as an approximate cube - up to, say, 6 feet on a side
    - powering and cooling it on two opposing faces
    - with water-cooled silver bus-bars the size of the faces
    - connecting it by covering the other four faces with optic fibers for I/O (to interconnect with integrated light-emitting and sensing devices).

    Of course the point of the yarn, in addition to potentially being possible, is the appearance of the resulting device:

    An enormous supercomputer in the form of a 6-foot cube of diamond, glowing slightly red from operating heat, supported by water-cooled silver bus bars in an inert atmosphere within a glass bottle (ala a vacuum tube), with millions of optic fibers to provide it with sufficient I/O.

    Just the sort of thing you'd find as a component in, say, one of the later Skylark spacecraft of E. E. (Doc) Smith's Golden-age SF stories.
  • I do not see anything about cooling. I mean if the transistor is 3d, this means the warmth is not only created by each part, but some part in the center generate warmth which has to travel toward the outside. Could not this be a big problem ?

  • Industry has been there, tried that (Score:3, Informative)

    by Ancient_Hacker ( 751168 ) on Tuesday July 19, 2005 @06:16AM (#13102054)
    this is mighty obvious... but lots of prroblems:
    • each layer of logic takes many steps of masking, diffusion, etching, washing. Each step, even if carefully done, kills a certain percentage of the chips. If you try adding another layer of logic, the yield goes WAAAY down, making the whole process uneconomical
    • You have a 2D-3D mismatch-- heat gets produced in 3D but carried off in only 2D. It's hard enough to cool one thin layer, much harder to keep two layers cool enough.
    • There's considerable capacitive coupling between the layers.. Signal rise times go blooeay, as does the signal to noise ratio. All bad things.
    • Even if you could build and test the layers separately, you still are going to lose chips in the bonding and wiring process.
    • IBM has been promising this kind of thing for about 30 years now. With ideas like frozen mercury for interconnects. Hasnt happened yet.

    • each layer of logic takes many steps of masking, diffusion, etching, washing. Each step, even if carefully done, kills a certain percentage of the chips. If you try adding another layer of logic, the yield goes WAAAY down, making the whole process uneconomical

      Thats exactly what I was thinking as I read through all these comments. Everyone is talking about cooling, etc. All I can think of is how bad the yield would be for a chip with multiple transistor layers. Sure, I may not have much knowledge as to t

  • Wow. (Score:2)

    by Gannoc ( 210256 )

    Its amazing what people are motivated to develop when they're confident that they are NEVER getting laid.

    (RPI Alums, you know what I mean.)

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