10-Petaflops Supercomputer Being Built For Open Science Community 55
An anonymous reader tips news that Dell, Intel, and the Texas Advanced Computing Center will be working together to build "Stampede," a supercomputer project aiming for peak performance of 10 petaflops. The National Science Foundation is providing $27.5 million in initial funding, and it's hoped that Stampede will be "a model for supporting petascale simulation-based science and data-driven science." From the announcement:
"When completed, Stampede will comprise several thousand Dell 'Zeus' servers with each server having dual 8-core processors from the forthcoming Intel Xeon Processor E5 Family (formerly codenamed "Sandy Bridge-EP") and each server with 32 gigabytes of memory. ... [It also incorporates Intel 'Many Integrated Core' co-processors,] designed to process highly parallel workloads and provide the benefits of using the most popular x86 instruction set. This will greatly simplify the task of porting and optimizing applications on Stampede to utilize the performance of both the Intel Xeon processors and Intel MIC co-processors. ... Altogether, Stampede will have a peak performance of 10 petaflops, 272 terabytes of total memory, and 14 petabytes of disk storage."
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If they used power-efficient ARM CPUs it could have been a Stampede of Hummingbirds.
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Don't bring technology concerns into a decision based on the neatest sounding name.
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High speed network interconnects can get a little toasty themselves, and the amount of glue logic/core would be rather higher with the smaller, fewer-cores-per-socket ARM beasties.
They might still win, I don't have numbers one way or another; but networking isn't free...(it would be interesting, of course, to see some ARM HPC design that fabbed a zil
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An extreme case would be brute-force crypto, in which the inter-node traffic is so low the entire supercomputer could be quite easily built on 10base2.
Looks like a cluster (Score:3, Insightful)
Not a supercomputer
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In there a distinct difference between the two?
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Don't ask me how I hit the N on the other side of the keyboard -_-
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There's a smooth-ish order of progression in terms of interconnect speed and latency(ie. SETI@home is a cluster; but inter-node bandwidth is tiny and latency can be in the hundreds of milliseconds, a cheapo commodity cluster using the onboard GigE ports has better bandwidth and lower latenc
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I know you're trolling but most supercomputers these days are computing clusters.
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From Wikipedia (http://en.wikipedia.org/wiki/Supercomputer)
Today, parallel designs are based on "off the shelf" server-class microprocessors, such as the PowerPC, Opteron, or Xeon, and coprocessors like NVIDIA Tesla GPGPUs, AMD GPUs, IBM Cell, FPGAs. Most[which?] modern supercomputers are now highly-tuned computer clusters using commodity processors combined with custom interconnects.
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Imagine a beowulf cluster of these clusters!
Explain (Score:2)
[title] Looks like a cluster [/title]
Not a supercomputer
Are you saying this because it is not a single system image, shared memory machine or because you just don't think distributed memory clusters are supercomputers?
I ask because I have built supercomputers and I find your comment puzzling, at best.
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Assuming you want to keep all of your compute nodes busy all the time, EC2 is not a good value.
They say they'll have several thousand servers. I don't know what a Zeus server is, but let's assume it's a 1U, 2 socket server and that they'll have 2000 of them. That will give them 2000 * 2 * 8 = 32,000 cores of CPU.
That's equivalent to 32000 / 4 = 8000 Amazon EC2 Quadruple Extra Large instances. Spot pricing right now matches Reserved instance pricing, $0.56/hour, so for $27M, they can get $27M / 8000 / 0.56 =
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rgb
What is a Dell 'Zeus' server? (Score:4, Informative)
The article mentions that it's using Dell 'Zeus' servers, but the only information I can find about those servers online is that they are being used to build this cluster.
What is a Dell 'Zeus' server?
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It's a codename for a server based on the Xeon E5 processors that aren't currently announced/generally available
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OK, OK.. I'll bite: But can it run Crysis... and imagine a Beowulf clust... nevermind!
What happens to 'old' supercomputers? (Score:1)
While I applaud (and always do) advances in supercomputers, it raises the question of what happens to the previous generation(s). I'd love to get my hands on even one of the blade based boxes in your usual configuration. Might not be good for the projected tasks in modern proposals, but they would be more than good enough for my modest needs. Anyone know who the surplus process works?
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The old computers probably just get sent to a scrap yard in China.
Actually, that makes you wonder what happens when they land there...
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No, this is an NSF Petascale "Track 2" project like TACC's earlier Ranger [utexas.edu] system or NICS [tennessee.edu]' Kraken [tennessee.edu] system, whereas Blue Waters was/is the NSF Petascale "Track 1" project. Same basic idea, slightly different pots of money.
(Disclaimer: I work for NICS.)
--t
LOL! (Score:2)
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Sounds like a sweet machine to run boinc apps on (Score:2)
Sounds like a sweet machine to run boinc apps on.
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Obligatory bitcoin comment.
Yes I new Meme needs to be born....
Bitcoin? HOW DOES IT FUCKING WORK!
Impressive if it were built today. (Score:4, Informative)
By 2013, 10 petaflops will be a competent, but not astonishing system. Probably top 10-ish on the top500 list.
The interesting part here will be the MIC parts, from intel, to see if they perform better than the graphics cards everyone is putting into super computers in 2011 and 2012. The thought is that the MIC (Many Integrated Cores) design of knights corner are easier to program. Part of this is because they are x86-based, though you get little performance out of them without using vector extensions. The more likely advantage is that the cores are more similar to CPU cores than what one finds on GPUs. Their ability to deal with branching code, and scalar operations is likely to be better than GPUs, though far worse than contemporary CPU cores. (The MIC cores are derived from the Pentium P54C pipeline)
In the 2013 generation, I don't think the distinction between MIC and GPU solutions will be very large. the MIC will still be a coprocessor attached to a fairly small pool of GDDR5 memory, and connected to the CPU across a fairly high-latency PCIe bus. Thus, it will face most of the same issues GPGPUs face now; I fear that this will only work on codes with huge regions of branchless parallel data, which is not many of them. I think the subsequent generation of MIC processors may be much more interesting. If they can base the MIC core off of atom, then you have a core that might be plausible as a self-hosting processor. Even better, if they can place a large pool of MIC cores on the same die as a couple of proper Xeon cores. If the CPU cores and coprocessor cores could share the memory controllers, or even the last cache level, one could reasonably work on more complex applications. I've seen some slides floating around the HPC world, which hint at intel heading in this direction, but it's hard to tell what will really happen, and when.
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This is what AMD is doing, lol. Once again, Intel gets scooped by a few years by a company that knows how to plan ahead.
56 gigabit InfiniBand (Score:2)
They claim they will use 56 gigabit InfiniBand. Has anyone tested Mellanox's FDR adapters and switches? From what I understand, that is 14 gigabit over 4x cabling. I remember all the problems just getting 10 gigabit to work over 4x 2.5 gigabit copper. I imagine this must use fiber to get any distance from the server to the switch.
Their asic seems to support only 36 ports. Building a 2000 node network with 36 port switches will take a lot of interconnected switches. I wonder what topology they are goin
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I know about this...I worked on the SilverStorm's Fabric Manager while I was there. I remember going into the VT System-X room and seeing piles of bad cables from earlier setup. If I remember correctly, the very first network had more switch ASICs than hosts...both were around 2000 or so. I think the first switches used 8-port ASICs internally. We made massive improvements to our fabric scan time and reaction time to moving cables, nodes going down, etc. This was a good thing because the non-silverstorm
But (Score:2)