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Data Storage Technology

Toshiba Plans To Ship a 1TB Flash Chip To Manufacturers This Spring (computerworld.com) 26

Lucas123 writes: Toshiba has begun shipping samples of its third-generation 3D NAND memory product, a chip with 64 stacked flash cells that it said will enable a 1TB chip shipping later this spring. The new flash memory product has 65% greater capacity than the previous generation technology, which used 48 layers of NAND flash cells. The chip will be used in data centers and consumer SSD products. The technology announcement comes even as suitors are eyeing buying a majority share of the company's memory business. Along with a previous report about Western Digital, Foxxcon, SK Hynix and Micron Technology have now also thrown their hats in the ring to purchase a majority share in Toshiba's memory spin-off, according to a new report in the Nikkei's Asian Review.
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Toshiba Plans To Ship a 1TB Flash Chip To Manufacturers This Spring

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  • by Anonymous Coward

    "Cheaper" is highly subjective, and while stacking dies with many layers does wonders for density, it does little for cost. If it were anywhere near the price of rotating magnetic storage, they would be honest and publish comparable units. Granted, one isn't going to put a hard disk in their cell phone, or expect the same performance, but NAND flash is still far from affordable for bulk storage, and probably never will be. Better technologies like 3D XPoint or memristors are more interesting and have muc

    • Good Grief, Charlie Brown, a REAL spring chicken.
      I remember MY first hard drive - a monstrous 5 MegaByte beast for a measly $150, which was half the price of the next cheapest drive on the market.
      Now, THAT was back in the days . . .
      when GMR (giant magneto-resistive heads) stood for 'Get Moving, Redneck!', a cops' final warning to shove off.
      and prices were expressed in cents per KILObyte.

      However, the woolly mammoth had sadly slipped away the previous year.

    • by dgatwood ( 11270 )

      Stacking dies with many layers might help bring cost down by letting you burn out fuses on defective dies and then do part binning based on the number of functioning dies. I'm not sure if the defect rates on flash would yield a significant benefit from doing so or not, though.

    • " it does little for cost"

      It does a lot for cost because you can double capacity without moving to the next process node.

      Any cost savings of a process shrink were due to the fact that the same capacity chip was half the size, therefore you got approximately ~2x the chips per wafer. This is useful for logic, but with storage no one wants the same capacity they want more capacity. Now with process costs eating away the chips per wafer gains, you're much better off staying with an old process if you don't need

    • by dmesg0 ( 1342071 )

      It does a lot for manufacturing cost (BOM only - not counting the equipment and fab costs). However it does nothing for the price, which is a matter of supply and demand, and currently has nothing to do with the manufacturing cost.

  • If they make it to spring as a company. In case people haven't been following, Toshiba is having a few money problems at the moment..
  • by fnj ( 64210 ) on Friday February 24, 2017 @09:25PM (#53927205)

    Idiot article confuses TB with Tb. So does the Toshiba press release. Morons.

    • by radarskiy ( 2874255 ) on Friday February 24, 2017 @09:50PM (#53927319)

      It's a package with 16 stacked die at 512 gigabits per die, which is 1 terabyte in total.

      It is (mostly) a mistake to refer that as a chip rather than a package, but there is nothing that is 1 terabit that is referred to as a terabyte.

      • When exactly did chip and package definitions change? I've been calling chips, well chips for over 20 years.

        Is there a guide to this, because it's making NAND discussion quite confusing online in general the last 18 months.

        • Words with multiple uses are extra bad with flash, since you also have the levels stored in an MLC bitcells, the levels of bitcells stacked on the die, and the die stacked in the package.

        • by tlhIngan ( 30335 )

          When exactly did chip and package definitions change? I've been calling chips, well chips for over 20 years.

          Is there a guide to this, because it's making NAND discussion quite confusing online in general the last 18 months.

          A chip is a die. A package is a collection of 1 or more dice/dies enclosed together and exposed as a set of pins. Memory these days often consist of multiple dice in a single package - the PoP (package on package) memory you see on a modern SoC is often a few dice in a package - there wil

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