Intel's Take on the Next Wave of Moore's Law (ieee.org) 22
The next wave of Moore's Law will rely on a developing concept called system technology co-optimization, Ann B. Kelleher, general manager of technology development at Intel told IEEE Spectrum in an interview ahead of her plenary talk at the 2022 IEEE Electron Device Meeting. From a report: "Moore's Law is about increasing the integration of functions," says Kelleher. "As we look forward into the next 10 to 20 years, there's a pipeline full of innovation" that will continue the cadence of improved products every two years. That path includes the usual continued improvements in semiconductor processes and design, but system technology co-optimization (STCO) will make the biggest difference. Kelleher calls it an "outside-in" manner of development. It starts with the workload a product needs to support and its software, then works down to system architecture, then what type of silicon must be within a package, and finally down to the semiconductor manufacturing process. "With system technology co-optimization, it means all the pieces are optimized together so that you're getting your best answer for the end product," she says.
STCO is an option now in large part because advanced packaging, such as 3D integration, is allowing the high-bandwidth connection of chiplets -- small, functional chips -- inside a single package. This means that what would once be functions on a single chip can be disaggregated onto dedicated chiplets, which can each then be made using the most optimal semiconductor process technology. For example, Kelleher points out in her plenary that high-performance computing demands a large amount of cache memory per processor core, but chipmaker's ability to shrink SRAM is not proceeding at the same pace as the scaling down of logic. So it makes sense to build SRAM caches and compute cores as separate chiplets using different process technology and then stitch them together using 3D integration. A key example of STCO in action, says Kelleher, is the Ponte Vecchio processor at the heart of the Aurora supercomputer. It's composed of 47 active chiplets (as well as 8 blanks for thermal conduction). These are stitched together using both advanced horizontal connections (2.5 packaging tech) and 3D stacking. "It brings together silicon from different fabs and enables them to come together so that the system is able to perform against the workload that it's designed for," she says.
STCO is an option now in large part because advanced packaging, such as 3D integration, is allowing the high-bandwidth connection of chiplets -- small, functional chips -- inside a single package. This means that what would once be functions on a single chip can be disaggregated onto dedicated chiplets, which can each then be made using the most optimal semiconductor process technology. For example, Kelleher points out in her plenary that high-performance computing demands a large amount of cache memory per processor core, but chipmaker's ability to shrink SRAM is not proceeding at the same pace as the scaling down of logic. So it makes sense to build SRAM caches and compute cores as separate chiplets using different process technology and then stitch them together using 3D integration. A key example of STCO in action, says Kelleher, is the Ponte Vecchio processor at the heart of the Aurora supercomputer. It's composed of 47 active chiplets (as well as 8 blanks for thermal conduction). These are stitched together using both advanced horizontal connections (2.5 packaging tech) and 3D stacking. "It brings together silicon from different fabs and enables them to come together so that the system is able to perform against the workload that it's designed for," she says.
"Moore's Law is about increasing the..." (Score:5, Insightful)
Re:"Moore's Law is about increasing the..." (Score:5, Informative)
Yeah it's ironic that a company who's own past CEO first proposed the observation that became of Moore's Law should no longer have any understanding of what he meant. Absolutely this strange attempt to redefine Moore's Law is absolute proof we hit the limit. We hit the physical limits of transistor density years ago.
Re: (Score:2)
Reading the entire statement - it sounds more like something I'd expect at an Apple / Google keynote. I have my doubts this person is an engineer - she's probably got a business background. Although then that begs the question why a manager would be speaking at an IEEE meeting.
Re:"Moore's Law is about increasing the..." (Score:4, Insightful)
Is it? Moore's law is the observation that the economically optimal number of components on a chip increases exponentially with time. It's not that unreasonable to say "increasing components" is about "integration of functions."
Meh (Score:2)
Slice up a bunch of dies and then stitch them together like Frankenstein's Monster?
To me, it sounds more like grasping at straws than a "pipeline full of innovation".
If there's anything left of Moore's law, it certainly looks it won't be at consumer price points.
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Slicing it up into pieces and stitching them back together has big advantages. You can mix different processes: use the newest, most expensive process for the logic cores, but an older, less expensive one for I/O. It also helps a lot with yields. If a monolithic processor contains a single defect, you have to throw it out. Split it up into four chiplets, and now you only have to throw out the one containing the defect.
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I don't know many details about "advanced horizontal connections (2.5 packaging tech) and 3D stacking" aside from some overviews over the years, but I would expect there might be some fabrication limitations.
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We will soon have the option to harvest our farts, so we can post & comment on stats about them.
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What do you mean by "damage it"?
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Like during assembly? Hopefully they can test the components before putting them together, but I don't know.
So they can build a single chip PC? (Score:2)
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Maybe that's why they did this:
"A key example of STCO in action, says Kelleher, is the Ponte Vecchio processor at the heart of the Aurora supercomputer. It's composed of 47 active chiplets (as well as 8 blanks for thermal conduction)."
This sounds suspiciously like bullshit. (Score:2)
When someone starts talking about "a pipeline full of innovation" then I start suspecting that the pipeline is filled with turds. The immediate benefit of this kind of stacking is cost reduction, but the down side is that you have to trust that these interconnections are robust. It's relatively safe to assume that Intel has a plan for how to get the heat out of the package successfully (these aren't the P54C socket-melting days, after all) but I wonder how well the connections between stacked chiplets are
Surprise Surprise (Score:1)
Let's hide the failures behind the curtain (Score:3, Interesting)
It's nice to talk about more efficient integration as a method of satisfying Moore's Law dictate. But the actual Intel failures, and the myriad patches needed to address serious flaws in their architecture, are being brushed under the rug.
Predictive instruction problems have caused constant patches to stanch the security risks-- new ones found almost every month. These risks are mitigated by firmware updates, but many vendors haven't implemented the fixes, increasing machine vulnerability to insane heights.
All the marketing gushing doesn't address these core problems with x86/64 design failures. ARM and RISC-V are breathing down their necks, and there are no cogent strategies to compete with these designs in a practical way; Intel's battleship takes years to change course. No Pat Gelsinger is going to change that problem.
They can talk a great story, but no one is doing actual battles with the demons.
AMD's chiplet design (Score:3, Informative)
Turn Out The Lights, Intel (Score:3)
I doubt this will convince Intel investors. Intel has had too many failures of late to win those investors back. Intel is adrift.
Dark silicon (Score:3)
This has been a trend for a while now. Transistor density has been increasing faster than the energy/transistor has been decreasing. That means you can pack more transistors onto your chip, but only if a smaller fraction are active at the same time.
The solution is to have lots of specialized circuits, each designed to do one function as efficiently as possible. It's ok if each one is rarely used. You need most of your transistors to be idle. It sounds like they expect this trend to accelerate, with more and more application-specific circuits each designed to accelerate one particular workload.
So to be perfectly clear about this (Score:1)
Intel is no longer pursuing the brute force processing that they used to shut out Motorola and now that Apple is producing compatible CPU's but specializing in the direction of the Motorolla CPUs having performance optimized instead of brute force, otherwise known as Apple silicon, Intel is changing their tune.
If you do not know this, then you are not old enough to know it!
Should it be any surprise Apple is doing this, given they know the difference in CPU's performance in their product line?
Intel? (Score:2)
What the fuck do Intel know about anything other than speeding things up by ignoring security?
Form follows function? (Score:2)
What an amazing insight. Congrats, Intel.
Say what? (Score:2)
"Moore's Law is about increasing the integration of functions," says Kelleher.
In case you're wondering, no, this woman does not have an MBA.