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IBM Hardware

IBM Says It Can Fit Nearly 100 Billion Transistors On a Chip (zdnet.com) 111

IBM has unveiled "what it says is the world's first sub-1-nanometer chip technology," reports ZDNet, "designed to pack nearly 100 billion transistors on a fingernail-size die, roughly doubling the density of IBM's earlier 2-nm test chip, first shown in 2021... Today, the smallest, most powerful chips top out at about 80 billion transistors." At the heart of the announcement is NanoStack. This is a three-dimensional, nanosheet-based transistor design that scales vertically, or along the z-axis, by stacking and staggering CMOS devices. Unlike today's nanosheet architectures, which IBM also pioneered and which are being adopted by leading foundries at 3 nm and 2 nm, NanoStack bonds two nanosheet transistors into a single vertical structure, with each tier optimized independently and contacted from opposite sides. Each transistor in the demonstrated structure uses three sub-5 nm-thick nanosheets, about "15 silicon atoms" across, separated by roughly 9 nm spacers. Two such devices are then bonded vertically using an ultra-thin dielectric process IBM describes as a key innovation. Because the top and bottom devices can use different channel materials, dielectrics, and metals, IBM argues NanoStack is less a single trick and more a transistor platform that can be extended through multiple generations: 7 angstrom (Å), 5 Å, 3 Å, and potentially down to 1 Å in its internal roadmap.

An angstrom, by the by, is one ten-billionth of a meter. In terms of chips, an angstrom is a tenth of a nanometer. "This is the world's first sub-1 nanometer chip technology with a new transistor architecture," said Jay Gambetta, Director of IBM Research and IBM Fellow, during a press briefing. "We're not just making smaller transistors, we're reinventing how chips are built to deliver dramatically more power and energy efficiency...." Based on internal benchmarking against its 2 nm node, the company said its new chips will deliver up to 50% higher performance at the same power, or up to 70% lower power for the same performance. Big Blue also highlighted a 40% improvement in the scaling of static random-access memory (SRAM) cell area relative to its 2 nm technology.

This is a change IBM described as a "step the industry hasn't seen in over a decade" and one that could be particularly important for AI accelerators that live or die on on-chip memory bandwidth... According to Huiming Bu, IBM's VP of silicon technology R&D, NanoStack is a new paradigm. It's moving chips to scaling fully into three dimensions and giving the industry at least "another decade" of logic advances as it crosses from nanometers into angstroms... The 40% SRAM density bump could also help architects push caches and on-die memory closer to compute units, cutting data movement overhead in training and inference workloads.

IBM sees a path to production use "in as early as the next 5 years", according to the article, and "expects NanoStack to eventually underpin CPUs, GPUs, mobile SoCs, and SRAM arrays."

IBM's VP of silicon technology R&D says the new innovation "can improve performance by 50% compared to the best available chip today, and at the same time can reduce power by 70%."

IBM Says It Can Fit Nearly 100 Billion Transistors On a Chip

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  • That's a one followed by eleven zeroes. Can you count that high?

    • Yes, if you give me more lifetimes.

      Can someone tell me if this is a 'good thing' so tjhat they can hardcode more algorithms, like AES, onto the chip?

      • by Kisai ( 213879 )

        The thing is, it's very hard to make electronics this small, as the current processes are basically still "lithography" techniques. A technique that goes back to etching acid into rock. Modern chip lithography evolved from photo lithography, the technique used to etch circuit boards.

        The ability to "draw" at sub-millimeter (1000 micron) requires using a light spectrum laser with a wave length small enough. So EULV is literately "extreme ultra violet" 13.5nm, which is basically x-ray wavelengths. Yes you hear

    • Can I use both hands?
    • Is that 100 billion transistors in that chip or are you just happy to see me?

    • Re:Wow! (Score:5, Funny)

      by bill_mcgonigle ( 4333 ) * on Monday June 29, 2026 @04:51PM (#66215982) Homepage Journal

      Interestingly enough if you count out loud your lips won't touch in the middle until you get to a million.

      Billion continues that deviation from the lower numbers.

  • by DeanonymizedCoward ( 7230266 ) on Monday June 29, 2026 @10:50AM (#66215516)

    While I like to come here and rant about stupidity and enshittification, this story gives me a moment to reflect on the amazing achievements we've made as a species. We long ago blew through the wavelengths of visible light, and are now encroaching on X-rays and approaching the sizes of some of the larger atoms with manufactured, active structures. Impressive.

    • Re: (Score:3, Informative)

      by tmetzcc325 ( 1149343 )

      I try to remind myself of things like this all the time. For every time you see some awful story on the news about things getting worse and people being awful to each other, remember that humans are also capable of things like building at the atomic level, sending people to and bringing them home from other celestial bodies, eradicating diseases, and creating masterpieces like the Night Watch and the ceiling of the Sistine Chapel. We're an amazing species and everyone needs to remember that now and then.

      • by dargaud ( 518470 )
        Yes, we can do things like that, so why can't we keep morons at bay ? We need (as a specie) a way to keep toxic people away from power and money and the possibility to ruin things for the rest of humanity. Pipe dream, I know.
    • by symbolset ( 646467 ) * on Monday June 29, 2026 @11:04AM (#66215538) Journal

      The transistors aren't actually smaller. It's standard in the field to market the next chip generation as a smaller size when they mean equivalent to the new size. In this case the transistors are stacked vertically so looking down you get layers X areal density of the 2 dimensional surface. We don't do this with flash stacks, which now have up to 321 layers and are mapped to 1000+.

    • by gtall ( 79522 )

      And I look at the environment and observe how we are heating ourselves to extinction along with most of the critters. Some plants may survive.

  • Using Z (Score:5, Informative)

    by symbolset ( 646467 ) * on Monday June 29, 2026 @10:54AM (#66215522) Journal

    The angstrom scale business is marketing fluff to make the density increase understandable to consumers. But this is one of the developments leveraging the Z dimension that are legitimate progress. The Z dimension gives more than just the same chip folded like origami. The net distance traveled by a signal in a cycle can be reduced, which yields massive improvement in performance without additional cost of power/heat.

    • by ceoyoyo ( 59147 )

      The angstrom scale business is marketing fluff

      Just like the nanometer business. Really, using a linear measurement to indicate density was not-what-you-think from the beginning, so toss micrometers in there too.

      make the density increase understandable to consumers.

      Consumers don't care. People contracting foundry services care.

    • The naming conventions have been marketing fluff for a decade or more at this point. At the end of the day no one really cares how the density gains were accomplished as long as it allows the chip makers to achieve the same performance as last year at a lower cost. The biggest breakthrough isn't going to be increasing the density as we've been doing for decades, but being able to do so without an exponential increase in cost for that company increase which effectively makes the performance per dollar graph
    • by dargaud ( 518470 )
      How to they evacuate the heat ? And with the size decrease, doesn't leak current increase, leading to more errors ? How did they solve that, particularly with a 10-fold jump ?
      • The transistors aren't actually smaller. They fit more of them in the same 2 dimensional area by using layers. The layers are the Z dimension. The thermals are an interesting question.

    • Re:Using Z (Score:4, Interesting)

      by paulpach ( 798828 ) on Monday June 29, 2026 @05:34PM (#66216034)

      In the old times, nanometer scale measured the length of the gate in a MOSFET transistor.
      When we switched away from MOSFET, it became a marketting term. 2nm node means: technology as efficient as a hypothetical 2nm MOSFET. There is nothing in there that is 2nm in size. The transistors are no longer getting smaller, instead they find ways to pack more of them together, such as routing the power from the bottom and building vertical structures (FINFET and GAA)

      Basically we use nanometer/angstrom scale to describe chip technology in the same way that we use horse power to describe engines.

      • by keltor ( 99721 ) *
        Horses sustain about 7-7.5 hp for longish periods of time. So the horsepower is itself kinda humorous.

        Endurance athletes can sustain about .3-.4 hp for incredibly long periods of time. Considering the fuel requirements even including allometric scaling, humans are actually more efficient than horses at producing horsepower. :D
    • Not completely true. Only a small portion of the power / heat comes from moving signals between transistors. The most significant amount comes from the transistor gate itself.

      Z stacking creates a very real problem in that heat concentrates more in a small space as there are multiple heat sources overlapping. Not only do you have more power/heat (though proportionally lower than a 2D layout) but you also have a requirement to move heat away from the source faster as hotspots would be more severe.

      We're alread

  • by caseih ( 160668 ) on Monday June 29, 2026 @10:59AM (#66215528)

    Definitely a promising path. Extracting heat becomes a challenge in 3D silicon.

    • And it has always been thus.

      Stacking is not new. Heat dispersion problems that kill it are not new. A chip when heat-dispersed with a heat sink apparatus has known characteristics, but non-linear things happen when you heat both sides without some kind of temperature control method; chips bend, and then strange things happen.

      This is news to cook the stock price, and maybe this generation of "advance".

  • IBM argues NanoStack is less a single trick and more a transistor platform that can be extended through multiple generations: 7 angstrom (Ã...), 5 Ã..., 3 Ã..., and potentially down to 1 Ã... in its internal roadmap

    How would that even work? Isn't single-Angatroem count basically the size of an atomic layer? What's there even left to make a circuit from?...

    • by Junta ( 36770 )

      Keep in mind it's not and hasn't been a specific measure of something in particular in a while. It's a rough analogy for how a traditional process would have to make gate length to achieve the same density. So it's impossible to make a gate length that small, but by taking other measures it is supposed to be "just like getting them that small".

      • ^this, it is mostly marketing and sadly the press pick up on the marketing angle for their headlines. It is still pretty cool but they are not that small, it is like putting 50 quarters stacked on top of each other and then saying you have fit 50 quarters into the size of a single quarter.
    • For quite a while now calling something an 'X-nanometer process' only implies the precision with which they can assemble the much bigger transistors and insulation gaps. It's like saying you can build a bridge with dimensions down to a centimeter but the bridge itself is many meters long.

      - Why yes the nanometer ratings are like that bridge they have to sell you.
  • by jfdavis668 ( 1414919 ) on Monday June 29, 2026 @11:32AM (#66215566)
    Sounds like something Dr. Evil would ask for.
  • Reminder of what I read in a magazine some decades ago, that the human brain utilizes just 25 to 50 watts and uses electric and chemical impulses while immersed in conductive fluid. When playing chess, a grandmaster can evaluate at best about 6 moves per second while a computer evaluates millions .. yet the computer is only two or three times better than a human.

    • by ceoyoyo ( 59147 )

      That must have been a while ago. Computers are effectively unbeatable at chess. One of the best programs was written by a Norwegian nerd in his spare time and then forked by an impatient Italian. It will run on your phone and will almost certainly kick your ass, although if you want to be sure of beating every human who's ever lived you might want to give it a desktop computer.

      • Re:Human brain (Score:4, Interesting)

        by backslashdot ( 95548 ) on Monday June 29, 2026 @04:57PM (#66215990)

        Yeah but the computer is running millions of move simulations, but a grandmaster is doing 1 millionth of that computation and still playing well. If we restricted the computer to only do a few thousand evaluations per second it would fail miserably. Same thing with self-driving a car. A human can learn with 20 hours of driving school, meanwhile the FSD training models need tens of billions of miles driven in simulation and all kinds of scenarios reasoned through for it.

        We're missing some fundamental thing(s) when it comes to computation. I have no idea what it is -- we only know that there's a way to do it but we don't know how. Somebody, or AI itself will figure it out soon (like within a century, maybe even a decade or two).

        • Well, one thing you're missing is the fact that when humans learn something, they don't start from scratch. The driving instructor teaches you not only the basic rules, but also empirical cues so that you can learn quickly. Ditto for chess, learned and self-obtained experience informs the grandmaster that some opening moves are better than others. Those others and their algorithmic children don't need to be checked. A computer brute forcing a problem like chess or driving will be lousy, but if you give it m
        • by ceoyoyo ( 59147 )

          No, the grandmaster is doing many, many more calculations, just in parallel instead of serial. The human is also not blindly searching a tree of possible moves but spending a lot of computation on figuring out which are promising branches to prioritize. Modern chess programs are so good because they do the same thing.

          A human can learn with 20 hours of driving school

          No, they can't. We don't generally let humans even attempt driving for something like 16 years. They're also pretty shit at it until they have a

  • by hcs_$reboot ( 1536101 ) on Monday June 29, 2026 @11:55AM (#66215598)
    IBM has been making big promises about semiconductors, quantum computing, and other technologies for years.
    It's a good way to keep the stock price elevated*.
    But what has IBM actually delivered in any of these areas in recent years?

    *like Sam Altman and AGI for instance
    • Copper interconnect and silicon-on-insulator were both pioneered by IBM. They have had serious semiconductor R&D over the years.

    • by Tailhook ( 98486 ) on Monday June 29, 2026 @01:08PM (#66215700)

      But what has IBM actually delivered in any of these areas in recent years?

      A great deal. IBM licenses, partners and consults with semiconductor manufacturers globally, and runs a thriving IP business from their huge R&D facility in Albany, NY. Samsung, Rapidus, AMD, ST, SMIC and others are all paying for IBM tech in recent deals. GlobalFoundries bought out IBM Microelectronics for IBM's 300mm tech. IBM is among the most prolific patent filers in the world.

      The real story here is this: ASML has a new machine for a new process node. ASML is obligated to perform much of their R&D in the US due to strict export and technology sharing agreements with the US government. IBM operates huge, world class R&D lab in Albany, heavily subsidized by the state and US government. The new process that this story is about is really IBM working as an R&D partner with ASML to refine the process and get it ready for commercial operation.

      In a few years, when they get the yields to something plausible, ASML customers will buy the new machines, and IBM will be in the room, taking their cut for IP, consulting, support etc.

      • ASML is obligated to perform much of their R&D in the US due to strict export and technology sharing agreements with the US government.

        It is not really. ASML's R&D divisions are based on regional expertise. The majority is still done in Eindhoven. In California there's an R&D hub looking at advances in EUV light sources and in Connecticut they focus on mirror fabrication (pun... get it?) while the majority of ASML's current equipment has mirrors developed by Zeiss. They do R&D the world over based on localised expertise, and for some components that happens to be in the USA. ASML does significant R&D in China too with a lot

    • A lot of the stuff IBM works on ends up in their mainframes so as a consumer you'll likely never hear about it. https://www.redbooks.ibm.com/r... [ibm.com]

    • by keltor ( 99721 ) *
      IBM is second only to TSMC and Intel in semiconductor advancements.
    • IBM invents the stuff that TSMC, Samsung, Intel, and the big fabless designers adopt. They are an important player in chip design, even if they don't own any fabs themselves. For instance they design their own mainframe chips.

      You're right that their claims on quantum computing have fallen flat - in fact that entire industry is going nowhere IMO. Their "Blue Jay" 2000 qbit is now slated for >2034 ffs. In their own charts they were promising >10k qbits by this year. All those old promises seem to be gon

  • >the company said its new chips will deliver up to 50% higher performance at the same power, or up to 70% lower power for the same performance.

    >IBM's VP of silicon technology R&D says the new innovation "can improve performance by 50% compared to the best available chip today, and at the same time can reduce power by 70%."

    One of these things is not like the other.
    • Heat and losses enter the equation. You could underclock you current CPU (by a lot) and almost forgoe having that active heatsink.
  • Um, what? (Score:5, Interesting)

    by CEC-P ( 10248912 ) on Monday June 29, 2026 @12:28PM (#66215634)
    IBM sold off its semiconductor business in 2014 and does not produce any chips themselves of any kind at all. They don't even make their own qubits. What they likely meant to say was that TSMC found a way to make 1nk chips or whatever ridiculous claim they're making that almost definitely isn't true.
    • by visorg ( 4521201 )
      Wrong. IBM manufactures its own qubits. Rather than outsourcing to external foundries, IBM creates superconducting transmon qubits at the advanced 300mm semiconductor fabrication facility located at the NY CREATES' Albany NanoTech Complex in New York. Thanks for your uninformed comment.
    • Re:Um, what? (Score:4, Informative)

      by im_thatoneguy ( 819432 ) on Monday June 29, 2026 @03:25PM (#66215900)

      It is in character for the tech giantâ"its research division produced the first prototype for a 2 nanometer node chip back in May 2021.

      With that development, âoewe highlighted the research, and now all leading foundries are manufacturing theseâ

      Just because they don't make it doesn't mean they can't license the patent to the foundries.

    • What IBM is referring to is the transistor design, from the sounds of it. That, and / or some sort of circuit layout that sounds like it eliminates the need for TSVs (through-silicon vias). Maybe they've invented a successor to FinFET, as well.

      So IBM may not manufacture, but they still design chips for their POWER series, and they also conduct R&D. The R&D group is where this research may have been conducted - if IBM can invent a radical new technology, it can win by licensing. Licensing is the high

  • Answer: Zero, they don't have a semiconductor business anymore. I'm much more impressed by what TSMC can do today than what a research group says they can do five years from now.
  • making it work reliably and being able to manufacture with good yields is an entirely different set of problems

    • So this technology should be showing up in a general purpose CPU chip about the time that Windows14 is available. I'm assuming that Microsoft is starting to work on cranking up the complexity of their OS and apps to ensure there are no left over cycles ....
  • "IBM is explicit that "0.7 nm" and "7 angstrom" should be read as generational node names, not literal gate lengths or pitches, in line with the broader industry trend of decoupling node labels from specific physical dimensions. Internally, the company said it benchmarked NanoStack's critical dimensions—such as gate pitches and contacted gate pitch—against a projected 1 nmclass node, then pushed scaling by going vertical."

    Someone needs to come up with a new nomenclature. What if ASML develops a

  • Checks date...yep usual IBM quarterly stock boosting article about something they might have in 5 years time if everything goes well. I guess it is at least a change from the usual Quantum computing puff pieces they publish.
  • Chip nerds, is "transistor" still a useful metric anyway? Aren't modern chips that much more advanced that splitting their compute into single transistors doesn't make sense?

    • A transistor is still the fundamental basic unit of all logic for chips. You can put transistors together to make different things like high-speed cache memory with flip-flops as well as all types of logic gates.

      DRAM memory is a bit different, only the high-speed cache(SRAM) is built from transistors. DRAM uses a capacitor to store a bit and is WAY WAY slower than SRAM which just keeps passing a bit back/forth between multiple transistors to store it.
      • by allo ( 1728082 )

        So there is no more efficient "building block" than combining transistors? I get the appeal of simplicity, I just would have thought that one might be slightly faster with a more complex element than by combining several transistors for some operations.

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