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Technology Hardware

Adapteva Announces Epiphany Mesh Processor 41

Posted by Soulskill from the new-dog-in-the-fight dept.
MojoKid writes "A new company, Adapteva, has announced its own entry into the field of many core, mesh-connected processors. The company's Epiphany architecture is an array of simple, RISC-based microprocessors. Each processor contains ALU and FPU units, 32K of SRAM cache and each processor node incorporates a router. Nodes communicate with each other via mesh networking. The implementation is capable of scaling up to a 64x64 array (4,096 processors). Adapteva claims that Epiphany is capable of delivering unprecedented performance per watt, with a 16-core array offering up to 19Gflops at 270mW on a 28nm process."
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Adapteva Announces Epiphany Mesh Processor More

Adapteva Announces Epiphany Mesh Processor

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  • It's not a stand-alone CPU (Score:3, Informative)

    by Anonymous Coward on Tuesday October 04, 2011 @03:20AM (#37596586)

    It sounds like something for a specific application:

    "Unlike other designs, however, Epiphany is designed to be an FPU co-processor, not an independent chip"

    • Re: (Score:2)

      by jhoegl ( 638955 )
      How Dare FP not be about some obligatory Skynet system, instead be all insightful and what not?!?!

      • That's because the news in this article is actually for geeks, not just news for nerds. The front page story is collapsed to nothing but a geeky headline, so there's a barrier to entry Slashdot doesn't usually offer.

        More of this, please.

  • obviously (Score:2, Funny)

    by Anonymous Coward

    http://xkcd.com/619/

  • Does this mean I should dust off my OCCAM textbooks?

    • Re: (Score:3)

      by slew ( 2918 )

      Does this mean I should dust off my OCCAM textbooks?

      No you should never dust off your OCCAM textbooks ;^) No language that requires a folding editor should be used to write modern software. Of course CSP is a fine model for programming, though...

      • It doesn't require a folding editor. However it did use indentation syntactically which was bizarre (and the compiler I used got confused with tabs). Python uses indentation that way too...

        • Re: (Score:2)

          by cynyr ( 703126 )

          I also find that doing OOP means a folding editor is just about necessary for me to work efficiently. Folding methods and classes makes others code much easier to glance through, as well as things i wrote a few years back.

    • Good god, I had to actually load a PDF [adapteva.com] to find out the answer. You use C in Eclipse and GDB for debugging.

  • Tilera has had 64 and 100 cores for a while now. (Score:3, Informative)

    by itsybitsy ( 149808 ) * on Tuesday October 04, 2011 @03:46AM (#37596670)

    Tilera has had 64 and 100 cores for a while now.

    "Tilera's primary product family is the Tile CPU. Tile is a multicore design, with the cores communicating via a new mesh architecture, called iMesh, intended to scale to hundreds of cores on a single chip. As of September 2010, shipping versions of Tile have 36 or 64 cores. The goal is to provide a high-performance CPU, with good power efficiency, and with greater flexibility than special-purpose processors such as DSPs. In October 2009, they announced a new chip TILE-Gx100 based on 40nm technology that features up to 100 cores at 1.5 GHz. Other Gx family members will include 16, 32 and 64-core variants."
    http://en.wikipedia.org/wiki/Tilera [wikipedia.org]

    64 Cores
    "TILE64 is a multicore processor manufactured by Tilera. It consists of a mesh network of 64 "tiles", where each tile houses a general purpose processor, cache, and a non-blocking router, which the tile uses to communicate with the other tiles on the processor. The short-pipeline, in-order, three-issue cores implement a MIPS-derived VLIW instruction set. Each core has a register file and three functional units: two integer arithmetic logic units and a load-store unit. Each of the cores ("tile") has its own L1 and L2 caches plus an overall virtual L3 cache which is an aggregate of all the L2 caches.[1] A core is able to run a full operating system on its own or multiple cores can be used to run a symmetrical multi-processing operating system. TILE64 has four DDR2 controllers, two 10-gigabit Ethernet interfaces, two four-lane PCIe interfaces, and a "flexible" input/output interface, which can be software-configured to handle a number of protocols. The processor is fabricated using a 90 nm process and runs at speeds of 600 to 900 MHz."
    http://en.wikipedia.org/wiki/TILE64 [wikipedia.org]

    100 Cores
    "The TILE-Gx processor family brings 64-bit multicore computing to the next level, enabling a wide range of applications to achieve the highest performance in the market."
    http://www.tilera.com/products/processors/TILE-Gx_Family [tilera.com]

    • This is more a GPGPU competitor. Tilera is designed for things like big web apps where you have lots of not particularly computationally strenuous tasks that need handling with relatively low latency. This is designed for the kind task where you want to use a GPU, but your algorithm doesn't fit. It would probably also be good at things like ray tracing.

      • It runs Linux which, last time I checked, works for general purpose computing. 100 cores... sweet.

    • Re: (Score:1)

      by gentryx ( 759438 )
      Tilera's chips don't have FPUs, they're therefore no good for most compute intensive applications (e.g. scientific computing, simulations...) We've seen on-chip networks, local scratch pads (read: caches) and FPUs on many previous chips. What sets this design apart is the combination of all three on a large scale. It's really like the IBM Cell BE, just not 1D, but 2D. Interesting.

  • Green Arrays GA144 Forth chip, 144 cores (Score:1)

    by Anonymous Coward

    Green Arrays [greenarrays.com] -- has 144 cores running Forth as their machine code, at about 700 (integer) mips per core, on a 20 dollar, 0.18 micron (180nm) chip. Built by a few guys including Forth inventor Chuck Moore on basically a shoestring budget. Each core has just 64 words of ram (18-bit words) but for some purposes that's all you need. Power consumption is around 0.5W with all 144 cores going and close to zero at idle. That's around 200 GIPS/watt though they're integer mips not floating point.

    • Re: (Score:2)

      by JanneM ( 7445 )

      Interesting idea; though I'm unclear exactly what kind of application would be a good fit for such a thing. I

  • Interesting... (Score:3)

    by fuzzyfuzzyfungus ( 1223518 ) on Tuesday October 04, 2011 @06:02AM (#37597044) Journal
    Sounds like the perfect chip upon which to build a modernized version of the coolest looking computer ever [mission-base.com]

    • Thanks for that. So little brain, so much to keep track of. When they came out, each in turn, I thought the Transputer and Connection Machine were the best tech since at-the-time-unrealized memristor.

  • (Im showing my age here!)

    Imagine a Beowulf Cluster of these!

    (Sorry , it was the voices!)

    N ...

  • Sounds neat, but what caught my attention was the misread "Adapteva Announces METH Processor." Oops, I thought it was going to be one heckuva an article. Still neat, though.

  • Anyone else remember back when you logged off, you were told how many flops you had used (because you paid for them) ?

  • Who cares! (Score:3)

    by sglewis100 ( 916818 ) on Tuesday October 04, 2011 @09:19AM (#37597992)

    Each processor contains ALU and FPU units, 32K of SRAM cache and each processor node incorporates a router. Nodes communicate with each other via mesh networking. The implementation is capable of scaling up to a 64x64 array (4,096 processors). Adapteva claims that Epiphany is capable of delivering unprecedented performance per watt, with a 16-core array offering up to 19Gflops at 270mW on a 28nm process."

    You anti-Apple morons just don't get it. It's not about the specs, it's about the design!

  • RISC was always good at SMP. Back in the day, that was its biggest draw. If they had a 28nm process it would have been unprecedented news. What is really interesting about this chip, IMHO, is the embedded router. It brings to mind the MPC860.

  • <shameless plug>

    I've got one of these on my desk as I write. I've actually been working with it for several months now, and it's pretty sweet. It's intended to be a DSP co-processor coupled to an FPGA. The company I work for (BittWare) [bittware.com] has invested heavily in Adapteva, and we are introducing some boards featuring a handful of 16-core Epiphany chips (which we have rebranded as "Anemone") and an Altera Stratix 5 FPGA.

    The tools are Linux-only at this point, but that's more than OK by me. I think

  • I just ran some quick numbers, and with an 8 inch wafer they can get more then 200 of these CPUs. Each die is so small that their yield should be very high. A run of just 5 wafers would be around 10,000 units. I think this is reflected in their pricing. The minimum order is 10 chips for $200 US. They have an eval board with two chips, 288 CPUs for $450. This seems a little steep given the raw CPU price.

    It will be a complete bitch to program. The native Forth is a tiny subset of standard Forth. There is

    • A TI DSP starter kit will cost you more, 450$ is pretty much par for the course.

      Just because it uses asynchronous logic doesn't mean sequential consistency is ever violated from the ISA point of view ... obscure timing errors will occur for the same reason they almost always do, bad programming.

    • you mean 1000 units for 5 wafers?
      • Oh and one other thing. If it ia at 28nm that means there are probably 19 to 23 masking levels. This means just to tape out the masks they have to spend about $200k - $300k and that doesn't include any revs that will have to occur. Remember, this is JUST for the reticles. Include all the CMP and all the other hundreds of steps, you're easily talking about a cool $1.3 to $1.5M.

        So they better run a lot of at least 18 wafers or so depending on yield.
        • Oh wait again, $20 bucks a piece? then they need about 375 wafers just to break even at 100% yield.
          • Moore is a wacky genius, so normal rules don't necessarily apply. For an earlier stage of this project, besides designing his own computer architecture to run his own minimal version of Forth called ColorForth, he also wrote his own CAD package in Forth. http://www.colorforth.com/vlsi.html [colorforth.com] Not only did he do his own CAD, but his own VLSI simulation. One of his goals was to use as few transistors as possible. I have no idea if any of this made it into this chip, but there is some chance that it did. If so, t

  • A while back, Google bought out a research company that was in stealth mode making chips. All we really know is that the founder of the company did a bunch of work in routed microprocessors.

    Google has a very strong reason to be interested in work per watt (and area). If searches run much better on custom ARM-ish network-ish chip clusters, we'll never notice. Intel might.

    Anyway, their guys though the approach was good enough for an acquisition.

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