Adapteva Announces Epiphany Mesh Processor

MojoKid writes "A new company, Adapteva, has announced its own entry into the field of many core, mesh-connected processors. The company's Epiphany architecture is an array of simple, RISC-based microprocessors. Each processor contains ALU and FPU units, 32K of SRAM cache and each processor node incorporates a router. Nodes communicate with each other via mesh networking. The implementation is capable of scaling up to a 64x64 array (4,096 processors). Adapteva claims that Epiphany is capable of delivering unprecedented performance per watt, with a 16-core array offering up to 19Gflops at 270mW on a 28nm process."

It's not a stand-alone CPU

[Anonymous Coward]

It sounds like something for a specific application:

"Unlike other designs, however, Epiphany is designed to be an FPU co-processor, not an independent chip"

Tilera has had 64 and 100 cores for a while now.

[itsybitsy]

Tilera has had 64 and 100 cores for a while now.

"Tilera's primary product family is the Tile CPU. Tile is a multicore design, with the cores communicating via a new mesh architecture, called iMesh, intended to scale to hundreds of cores on a single chip. As of September 2010, shipping versions of Tile have 36 or 64 cores. The goal is to provide a high-performance CPU, with good power efficiency, and with greater flexibility than special-purpose processors such as DSPs. In October 2009, they announced a new chip TILE-Gx100 based on 40nm technology that features up to 100 cores at 1.5 GHz. Other Gx family members will include 16, 32 and 64-core variants."
http://en.wikipedia.org/wiki/Tilera [wikipedia.org]

64 Cores
"TILE64 is a multicore processor manufactured by Tilera. It consists of a mesh network of 64 "tiles", where each tile houses a general purpose processor, cache, and a non-blocking router, which the tile uses to communicate with the other tiles on the processor. The short-pipeline, in-order, three-issue cores implement a MIPS-derived VLIW instruction set. Each core has a register file and three functional units: two integer arithmetic logic units and a load-store unit. Each of the cores ("tile") has its own L1 and L2 caches plus an overall virtual L3 cache which is an aggregate of all the L2 caches.[1] A core is able to run a full operating system on its own or multiple cores can be used to run a symmetrical multi-processing operating system. TILE64 has four DDR2 controllers, two 10-gigabit Ethernet interfaces, two four-lane PCIe interfaces, and a "flexible" input/output interface, which can be software-configured to handle a number of protocols. The processor is fabricated using a 90 nm process and runs at speeds of 600 to 900 MHz."
http://en.wikipedia.org/wiki/TILE64 [wikipedia.org]

100 Cores
"The TILE-Gx processor family brings 64-bit multicore computing to the next level, enabling a wide range of applications to achieve the highest performance in the market."
http://www.tilera.com/products/processors/TILE-Gx_Family [tilera.com]