More AMD K7 details

AMD has released new details about the the K7. It will try to decode 3 x86 instructions per cycle (usually there are limits such as the number of bytes each of the three instructions can take). It will use dynamically scheduled speculative and out of order execution in each of its 3 integer pipes and each of its 3 MMX pipes. Every MMX instruction will have a 1 cycle throughput, although ensuring no stalls due to latency will be left up to the programmer. It'll have an even bigger Branch Prediction Table (2048 entries) nad a 12 entry return stack. It will use two 64Kb L1 caches (Instruction and Data split), each 2-way Set Associative, and two multi-level TLBs (24/256-Entries for Instructions, and 32/256-Entries for Data). As previously known the L2 cache will be backside, but will support sizes of 512Kb to 8Mb, and the 64bit system bus will run at 200Mhz. As with the K5 and K6, rare x86 instructions are left to the equivalent of microcode, while common x86 instructions decode to a few "Ops". A nice picture of the whole architecture is here, and yes it will do SMP. Thanks to six.