Microprocessor Forum wrap-up

Although processor vendors have been touting increased MHz for higher performance, this source of speed is almost tapped out. For instance in the 1GHz speed range, the number of gates that can be used for each stage of the pipeline is severely limited. Instead processor vendors will have to turn to exploiting parallelism to gain power: Intel, HP and AMD are targeting instruction level parallelism with EPIC and macro-ops/deep pipeline buffering respectively. Alpha and IBM are targeting both instruction level parallelism and thread level parallelism with either a very fast on-die communications protocol with other cores (Alpha) or multiple cores on a single die (IBM). This EETimes article also reveals how IA32 will be supported on Merced (IA32 to IA64 translation, like x86 to RiscOps in the PII/K5/K6).