Want to read Slashdot from your mobile device? Point it at m.slashdot.org and keep reading!

 


Forgot your password?
Close
typodupeerror
×
Technology Hardware

AMD Licenses Z-RAM Technology 191

Posted by Zonk from the anything-is-better-with-a-z dept.
ZuperDee writes "It appears AMD has licensed Z-RAM technology from Innovative Silicon for possible use in future processors. According to the article, this could lead to caches about 5 times denser than the SRAM that is normally used right now. C|Net says they will probably make the announcement on Monday."
This discussion has been archived. No new comments can be posted.

AMD Licenses Z-RAM Technology More

AMD Licenses Z-RAM Technology

Comments Filter:

  • The message is clear: (Score:5, Funny)

    by THE MESSAGE IS CLEAR ( 947711 ) on Saturday January 21, 2006 @04:28AM (#14525326)
    We have run out of ram letters!

  • Apple should have considered? (Score:3, Interesting)

    by Saven Marek ( 739395 ) on Saturday January 21, 2006 @04:32AM (#14525338)
    Another reason Apple's alliance with Intel wasn't such a good idea. Should have gone AMD, Steve.
    • it's x86 instruction set (even 64bit version) - so a switch sooner or later still is possible.

    • Can Intel not license the same Z-RAM patents?

      • Re:Apple should have considered? (Score:5, Informative)

        by Jace of Fuse! ( 72042 ) on Saturday January 21, 2006 @05:41AM (#14525497) Homepage
        They can, but probably won't.

        As many like to point out, Intel often shows a "Not Invented Here" attitude.

        It took a while for Intel to adopt copper interconnects, and they did that quietly when they finally caved.

        As far as I know, they still aren't using Silicon On Insulator.

        • As many like to point out, Intel often shows a "Not Invented Here" attitude.

          Quite. The crossbar switch came and went (1990's RISC workstations, appeared in the AMD Athlon) and intel's still using a 1970's bus for it's "high-end" pentium processors.

          Now we have point-to-point interconnects (1990's supercomputers NUMA architecture) called Hypertransport and intel's still flogging the 1970's bus on the pentium.

          Look at how pentium doesn't scale in SMP systems. Itanic is a different matter, but you can buy se

          • Someone needs to administer the clue bat at intel before it's too late.

            Apple? They have rights to HyperTransport, IIRC. Their engineers know which way is up.
            • Did Apple buy DEC from HP? Compaq bought them 5-10 years ago, and I thought HP still owned them?
              • Did Apple buy DEC from HP? Compaq bought them 5-10 years ago, and I thought HP still owned them?

                Sorry, I don't understand the point you're trying to make.

                These are the founding members of the HyperTransport Consortium:

                Advanced Micro Devices, Alliance Semiconductor, Apple Computer, Broadcom Corporation, Cisco Systems, NVIDIA, PMC-Sierra, Sun Microsystems, and Transmeta.

                Maybe you're referring to the Athlon bus similarities to the Alpha EV6/EV7 bus? But Alpha was sold to Intel years ago. The CSI bus may be b

        • Do I need to say more? OK, I guess I can - EMT64? StrongARM? (Yes, they bought that from DEC, but rather than kill it and go with one of their own designs they stuck with the better design. The StrongARM lives on in the PXA series.)

          As another person pointed out, SOI may simply be too expensive for Intel to license from IBM. Does AMD use SOI? I don't believe so.
          • Yes, they do. Their current 90nm process is SOI.
          • As another person pointed out, SOI may simply be too expensive for Intel to license from IBM. Does AMD use SOI? I don't believe so.

            The Z-RAM technology only applies to SOI. Without SOI, the entire basis on which it works simply doesn't exist.

            • You know what? I don't care. I want 2 16M DDR ZRAM chips in my computer RIGHT THIS SECOND.

              • You know what? I don't care. I want 2 16M DDR ZRAM chips in my computer RIGHT THIS SECOND.

                Good luck with that. I seem to recall having heard that they had some test wafers run at a couple of different fabs, but I don't think they intended them for sale, only testing. While I don't think there's a lot of reason they couldn't be built as separate chips, it'd be awfully hard to compete with the bulk DRAM manufacturers.

                Just for example, once upon a time you could buy DIMMs of memory from Enhanced Memory

          • Yes, AMD does use SOI technology in their recent processors, Licensed from IBM.
      • They could, but as of right now Intel is not using a Silicon on Insulator process like AMD and IBM are.
        Considering SOI is a prerequisit for Z-RAM, and how much fab capacity Intel has (they're stuffing 4MiB of total L2 onto their dual core 9x0 line right now), I wouldn't expect it to be high on their to do list.

    • Comment removed (Score:5, Interesting)

      by account_deleted ( 4530225 ) on Saturday January 21, 2006 @05:57AM (#14525525)
      Comment removed based on user account deletion
      • Yeah, just like they switch between ATI and NVIDIA for graphics chips. The company with the better priced product wins (if it can deliver the quantities).

      • Apple's already been down the road of choosing the apparently spiffier processor from a vendor that wasn't able to deliver in quantity.

        It's pure, unmitigated bullshit to claim AMD can't deliver processors in quantity. They have not experienced shortages, are expanding their facilities, and have contracted with a 3rd party to produce cores in the even that demand exceeds capacity.

        Intel, OTOH, is the one who has recently been having shortages, and was unable to produce enough chips to fill current demand, le

    • there's a lot of assumption there... (Score:5, Interesting)

      by YesIAmAScript ( 886271 ) on Saturday January 21, 2006 @11:50AM (#14526635)
      Note that if ZRAM works, it would let AMD put something like 4X as much cache on their chips in the same die area. This indeed would be quite a competitive advantage.

      But why do people assume this will work? There's a couple companies trying to do this stuff (T-RAM is another) and none have succeeded yet.

      It has proven to be difficult to get this kind of technology working in production chips. The main difficulty is that process control becomes very very important. Your yields drop through the floor.

      Additionally, note that any 1T transistor technology is inherently a stored charge device (like EPROM, EEPROM or flash memory but different). The problem is that transistors on chips are getting so small that they have less than 100 electrons in the gate of a transistor. So your insulating ability becomes very important. Your chip is designed for electron mobility that electrons can flow around a fairly long loop (the instruction execution path) 1 million times in 1 millisecond. And now you have to make sure that 100 electrons sitting in one place don't leak out in that same time.

      It's a challenge. It might be possible. I don't see any particular reason to think that AMD is going to be the one to do it though. Intel are wizards at process technology, as evidenced by their movement to 65nm before AMD. They don't happen to use SOI though, that's about the only advantage AMD has in this situation that I can see.

      Anyway, I do like AMD (I'm typing this post on one), but them licensing some unproven technology from a 3rd party is no kind of condemnation of Intel or Apple's choice of Intel.
      • Mod parent up 'Informative'. Not too many people already know about low-level logic physics.

      • It has proven to be difficult to get this kind of technology working in production chips. The main difficulty is that process control becomes very very important. Your yields drop through the floor.

        One of the major advantages of Z-RAM is that it doesn't require changes in the process (providing you're already using SOI, obviously). It doesn't seem to tighten the requirements on process control compared to a more conventional design either.

        At the same time, it provides a substantial increase in memor

        • Nope, it's a charged-base device like eprom or flash; the charge is on a floating gate, not a trench capacitor. Grandparent got it right.

          • Nope, it's a charged-base device like eprom or flash; the charge is on a floating gate, not a trench capacitor. Grandparent got it right.

            The charge is in a floating gate, but it needs regular refreshing or the value will be lost. This is essentially identical to a normal DRAM and completely different from a Flash, EPROM or EEPROM (which retain charge without refresh or even power at all).

            A DRAM doesn't necessarily use a trench capacitor either. Some do, but just for one other obvious example, there

        • Here's a point by point refutation of your arguments.

          "One of the major advantages of Z-RAM is that it doesn't require changes in the process (providing you're already using SOI, obviously). It doesn't seem to tighten the requirements on process control compared to a more conventional design either."

          That's untrue. You may not have to change the process, but you definitely have to tighten it. The amount of charge that you can hold on the gate becomes critical. The "leakiness" of transistors isn't nearly as im
          • You're just plain nutty.

            Coffin's law (inspired by Godwin's law): As an online discussion grows longer, the probability of an ad hominem attack approaches 1. As with Godwin's law, by making the ad hominem attack, you've ended the thread and automatically lost the argument on all counts.

    • '' Another reason Apple's alliance with Intel wasn't such a good idea. Should have gone AMD, Steve. ''

      Any idea what the performance and price characteristics of ZRAM are, or are you just a clueless AMD fanboy?
    • Lately, every Apple story attracts a few of these "should have gone AMD" posts. IMHO, at the time of the choice, ~ 1 year ago, there were two legitimate reasons to choose Intel over AMD.

      First and most importantly, Apple needed better laptop chips. And at the time, the Pentium M was miles ahead of the AMD mobile chips (and the IBM PowerPC chips) -- the difference has narrowed, but even then, the Turion 64 chips are relatively untested, relatively unavailable, and relatively higher in power consumption,
    • I'm sure that if that technology really make some difference, Intel will be able to licence it too. No problem here.

      Also, Intel has the best mobile processors, and what Apple really needed was a mobile processor.

      Based on this, I think that Apple did the right thing.

  • Details (Score:5, Informative)

    by Savantissimo ( 893682 ) * on Saturday January 21, 2006 @04:37AM (#14525348) Journal
    It's a single-transistor capacitorless memory cell using the "floating body effect" of silicon on insulator (SOI) devices. Presumably stored charge in the gate affects the operation of the transistor in a way that can be used to store and read a bit, but I didn't feel like registering to read the white paper. The new memory should be six times denser than SRAM and twice as dense as DRAM.

    • From teh Google (Score:5, Informative)

      by TubeSteak ( 669689 ) on Saturday January 21, 2006 @05:06AM (#14525411) Journal
      http://www.google.com/search?q=zram [google.com]

      A nice techy article about how/what makes ZRAM special. It goes in-depth about the things you mention. http://www.cieonline.co.uk/cie2/articlen.asp?pid=5 18&id=5434 [cieonline.co.uk]

      Obligatory Wikipedia Link [wikipedia.org]

      • Re:From teh Google (Score:4, Informative)

        by Savantissimo ( 893682 ) * on Saturday January 21, 2006 @05:26AM (#14525470) Journal
        Good article, thanks.

        It looks like there are no speed tradeoffs and it scales even better than DRAM, proven at 45 nm and suitable for 22 nm as well. AMD says such improvements usually take two years to show up in products, so that will still be 65 nm mostly with some 45nm. At 45 nm scale, a 1 cm^2 chip that is 70%-75% ZRAM would have about 48 MB.
        • Query:
          Why, if chips are becoming smaller and cooler, has the 'computer-on-chip' concept not hit mainstream?

          I mean, seriously. Tell me you wouldn't like to plug a 2cmx2cm chip into a 4cmx4cm mobo and have two ide chanels, two usb ports, a video port, an ethernet cable and a power input feed.

          Sorry. I geek out for the small computers, and I WANT THEM SMALLER!!!
        • Cant wait till our HDs have 128meg cache
          DVDRW built in 64meg
          digitaltv card - 64meg
          128meg in the ipod
          • The hard drive cache is probably the biggest deal. When you make CPU cache larger you have to do a bunch of work to be able to efficiently use a larger cache. Disk cache does not suffer from this problem, it just gets better as you get more memory. From what I've heard, hard drives from two or three YEARS ago should have had 16 or 32MB caches to really get peak performance, and they're still dicking around with 8MB, and maybe 16MB max now? When drives have twice the capacity and are more likely to have a hi

    • Re:Details (Score:3, Interesting)

      by Savantissimo ( 893682 ) *
      That should mean about 25 bits per square micron in a 65um process or 3.25 megabytes of memory per square millimeter. Pretty cool.

    • The new memory should be six times denser than SRAM and twice as dense as DRAM.

      You probably meant that it is six times denser than SRAM, but only half as dense as DRAM (that's still very good!). Typically, DRAM is approximately 12-50 times denser than SRAM

      , because each SRAM cell needs a lot of transistors and capacitors, and a DRAM cell only needs a capacitor and bitline connections.
      • Acording to the articles, SRAM uses 6 transistors per bit and DRAM uses 1 capacitor and one transistor, while ZRAM uses just one transistor, so ZRAM is indeed supposed to be twice as dense as DRAM. The transistors scale down better than capacitors, making new process scales more easily and cheaply achievable, so ZRAM is likely to replace DRAM in main memory. Memory is a tough, low-margin business where costs per bit depend mostly on bits/area, so doubling density is something that competitive manufacture
        • Ah, thanks for the clarification. I got puzzled by the ridicuosly low suggested SRAM/DRAM density relation. In reality, it's nowhere near 6/2... The SRAM needs tons of interconnects and stuff that really make them horribly ineffecient in space usage.

    • Re:Details (Score:3, Interesting)

      by darkmeridian ( 119044 )
      Finally, a technology patent that does some good! A small company innovated a new technology and licensed it to a big company that will bring it to market. Everybody wins! How rare is this?

      • Re:Details (Score:2, Interesting)

        by Short Circuit ( 52384 ) *
        More often than "A small company patents something, and sues big company for failing to pay for using it."

        The two are often related.

  • Dugg Earlier... (Score:4, Informative)

    by Fusen ( 841730 ) * on Saturday January 21, 2006 @04:38AM (#14525350)
    This is another article covering the licensing which was on digg.com earlier http://www.eetimes.com/news/semi/showArticle.jhtml ;jsessionid=V2AQAAYC3GVIQQSNDBESKHA?articleID=1771 01749 [eetimes.com]

  • Comment removed (Score:4, Interesting)

    by account_deleted ( 4530225 ) on Saturday January 21, 2006 @06:13AM (#14525552)
    Comment removed based on user account deletion
    • system ram is already dram, which is also single transistor memory - not nearly as much size savings, and if the dynamic power requirement rises at all, system manufacturers would probably be slow to adopt
    • That's a great idea. The Wikipedia article on Z-RAM mentions this.

      Because Z-RAM can scale much better than DRAM, they should be able to make it much smaller/faster. Also, because it is made of one transistor and not one transistor and one capacitor, it takes up half as much space. So you could double the density of your DRAM products.

      But more interesting, if this can replace SRAM that means that it doesn't require refreshing like DRAM does. This would be a MAJOR benefit if it replaced DRAM for system RAM.

    • Because it requires the new SOI process which is more expensive than the standard CMOS processes. Currently DRAM probably doesn't use these more expensive processes (because they don't need to be as fast) so changing to ZRAM would be more expensive.

  • Oblig. Futurama, of course (Score:5, Funny)

    by Dachannien ( 617929 ) on Saturday January 21, 2006 @07:08AM (#14525657)
    Organ Dealer: Z is just as good. In fact, is better. Is two more than X.

    • The AMD is good. The Intel is evil. The Intel shoots Dells, and makes new heat, and poisons the earth with a plague of IT 'consultants', as once it was. But the AMD shoots death, and purifies the Earth of the filth of bank switching. Go forth... and kill!

  • AMD Engineering vs Intel Marketing (Score:4, Informative)

    by sanman2 ( 928866 ) on Saturday January 21, 2006 @10:08AM (#14526207)
    Well, it's a sign that market leader Intel has over the decades drifted more towards marketing machine mentality, while challenger AMD has stayed somewhat truer to its engineering roots.

    Intel went for Itanium, while AMD went for 64-bit x86.
    Intel went for Rambus, while AMD went for DDR and HyperTransport.
    If you look at the multicore technology AMD is researching, it looks better than Intel's multicore.

    I'll acknowledge that Intel recognized the value of wireless ahead of AMD, although dedicated wireless chipsets are obviously better than Centrino anyway.

    I'm just glad that healthy competition is there, to make us consumers the ultimate winners.

  • Interesting use of an SOI "feature" (Score:5, Informative)

    by pm ( 11079 ) on Saturday January 21, 2006 @11:48AM (#14526626)
    In a nutshell, on a CMOS transistor on an SOI process (such as used by AMD and IBM, but not used by anyone else that I can think of... Intel, TI, TSMC, NEC, Samsung, etc), the delay of the transistor (how fast the transistor is) depends on the history of the signals that were applied previously to the terminals. So the transistor has a memory of previously applied values. Which, now that I write this, seems like it's obvious that this would make a possible memory storage element, but normally this "feature" is a major pain - because it's difficult to track the history of signals on a transistor using current CAD tools for, for example, determining the speed of the final design, you have to assume the worst case (so that your chip works no matter what).

    So normally this "feature" is considered a liability, or at least something that designers wish could be an asset but which is too hard to utilize effectively and is thus ignored.

    In more gory details, this exerpt from EETimes explains it pretty well:
    ( http://ww.eetimes.com/issue/bb/showArti...D%3D5730 0076+body+hysteresis+soi&hl=en [eetimes.com] )
    In partially depleted MOS transistors -- the only kind used in production SOI today -- the body of the transistor is a small, electrically isolated piece of silicon trapped between the active portions of the transistor and the insulating layer underneath. If this body is allowed to float, it will take on a voltage determined by the capacitive coupling between it and the other portions of the transistor. But the voltage -- or, more properly, charge -- on this floating body can affect threshold voltage, and hence the drive current, of the transistor.

    Ideally, the floating-body effect can deliver a formidable performance gain. Two circumstances arise from that gain, Soisic's Pelloie said. First, the voltage on the body influences the transistor's threshold voltage. "If you switch the gate of the transistor from off to on, then the body potential increases, which yields a decrease of the threshold voltage and then an increase of the drive current," he said. "The switch is then faster than in the bulk CMOS case, where the body is grounded."

    The second effect is another mechanism for influencing the threshold voltage. "When you use stacked transistors in a gate, like NAND, NOR and any other combinational gate with multiple inputs, the body-to-source voltage of the transistors corresponds to a forward-bias condition, and the threshold voltage is lowered," Pelloie said. "For bulk CMOS or in a grounded-body situation, if the source has a high voltage value, for instance Vdd [the power supply voltage], the body source voltage then becomes - Vdd and the transistor body source junction is reverse-biased." That increases the threshold voltage and lowers the drive current. Analyzed at the circuit level, he said, these two SOI advantages are combined and globally yield a higher-speed operation.

    But there is a catch to these threshold-voltage-lowering mechanisms, as Pelloie explained: "Since the body is floating, it follows the variation of the other terminals of the transistor. The body voltage never keeps the same value, as the transistors are, most of the time, switching in normal operation mode. This results in what we call the history effect: The propagation delay and some other features of the gates depend on the history of the signals applied to their terminals."

    -------- end EETimes snippet -----

    It will be interesting to see how this particular use of the floating body effect scales as we continue to move to 45nm and beyond. It will also be interesting how it handles low-voltage quantum-induced soft-errors. Also, similar to DRAM, this type of memory will need to be refreshed - if AMD uses it in a design, it will interesting to see how the impact of refreshing, and trying to read a very small effect and amplify it to make a signal will impact the speed of the devices when used in a large cache array.
  • I've read that chips like PowerPC 970 that have an extremely small die can be hard to cool, and also that cache is a good way to increase the size of the die without increasing power usage that much.

    If AMD can provide a reasonable cache that only requires a fraction of the die space, might this become a problem?

Slashdot Top Deals

To be awake is to be alive. -- Henry David Thoreau, in "Walden"

Close