100x Denser Chips Possible With Plasmonic Nanolithography 117
Roland Piquepaille writes "According to the semiconductor industry, maskless nanolithography is a flexible nanofabrication technique which suffers from low throughput. But now, engineers at the University of California at Berkeley have developed a new approach that involves 'flying' an array of plasmonic lenses just 20 nanometers above a rotating surface, it is possible to increase throughput by several orders of magnitude. The 'flying head' they've created looks like the stylus on the arm of an old-fashioned LP turntable. With this technique, the researchers were able to create line patterns only 80 nanometers wide at speeds up to 12 meters per second. The lead researcher said that by using 'this plasmonic nanolithography, we will be able to make current microprocessors more than 10 times smaller, but far more powerful' and that 'it could lead to ultra-high density disks that can hold 10 to 100 times more data than today's disks.'"
dense? (Score:4, Funny)
what ever happened to smart chips?
that's great and all. (Score:3, Insightful)
The problem is this: when will it be cheap enough to be used as a process for the chips we use now?
5-10 years (Score:4, Funny)
Re:5-10 years (Score:5, Funny)
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Re:5-10 years (Score:5, Funny)
very good news for you, electricity by fusion is no longer something promised 30 years away, now it's fifty.
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Re:5-10 years (Score:5, Insightful)
And artificial intelligence. That's always 20 years away.
No, it starts off at 20 years away and gets closer, and once it's less than 5 or 10 years away, someone redefines it and it's back to 20.
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Huh? AI has been over-promising and underdelivering since from day one, when its founders (McCarthy, Minsky) defined its aim and scope.
Now you are trying to rewrite this into "it is not that we are failing, it is that the goalposts keep moving". Are you a spin doctor for the republican party by any chance?
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Yeah, look, sorry it's early and that's the best I got at the moment. Live it up!
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I don't get it. Maybe I'm not supposed to, though, since I'm a Microsoft programmer and I see you mentioned those.
Space elevators (Score:5, Informative)
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So according to both of your estimates, great nuclear fusion is 35-40 years away. Of course, 30 years from now, we'll have mediocre nuclear fusion.
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Which is just in time for Duke Nukem: Forever.
30 years for hydrogen infrastructure (Score:1)
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And DNF...
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Fragility (Score:5, Interesting)
A question for the physics people out there.
At what point does Brownian motion become a serious consideration? What about tunneling electrons and other quantum-ish effects?
Re:Fragility (Score:5, Informative)
That's kinda the whole point (Score:3, Interesting)
Well, that's kinda the whole point. Given that today's transistors are 45nm or so, 10 times smaller would be 4.5nm, or about 15 silicon atoms IIRC. I think we can worry about that already.
Tunneling/Quantum effects: ~10nm (Score:3, Informative)
the researchers that make 200-400GHz transistors today DO in fact worry very much about tunneling. (I'm thinking of InP/InGaAsP transistors)
Quantum wells are around 5-10nm wide, so anything approaching ~20nm would at least have to account for that sort of quantum effect. So density may have a difficult limit to breach, but smaller lithography certainly makes high speed transistors easier to implement on CMOS.
(EE, not physics)
Re:Fragility (Score:5, Interesting)
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Re:Fragility (Score:5, Informative)
Here is an article on it. Although its from 2006, there has been more work done on it. There are more articles on it in the literature.
If you search for 'self healing' microprocessors you can find a number of articles on it.
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So bit rot is real now? Argh.
Well, at least I can put it back on the excuse calendar.
Not true (Score:1, Informative)
This is completely untrue, if a transistor fails on a CPU, that's it, there's no routing around the damage as you seem to imply.
If you'd actually read the article you referenced when queried by someone else, you'd see that was a three year study initiated in 2006, so even if that study bears fruit it'd be 5-10 years at least before it showed up in the CPUs you buy from Intel or AMD.
Re:Fragility (Score:5, Insightful)
At about 5nm. Other effects should limit our current tech to about 10nm.
If "10 times smaller" is about chip area, then it might be possible - square root of 10 is about 3 and our current best lithography processes are about 30nm.
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Thermal diffusion of atoms in a device do cause problems and limit the temperature at which semiconductors can work. In fact, diffusion of dopants is one way a chip can 'wear out' with long term use. No doubt the smaller the scale the more problem diffusion will be, but it tends to be very temperature sensitive, so keeping the device at some reasonable temperature would pr
Re:Fragility (Score:5, Informative)
Tunneling electrons and other quantum effects are already in effect in current devices. We just design around those effects instead of taking advantage of them currently. When we really get the ability to make reliable 5nm size scale parts, we'll just switch to quantum dot based transistors (single electron transistors).
Brownian motion isn't relevent here.
A big issue is that sharp features are thermodynamically unstable (lots of dangling surface bonds), so edges tend to "soften" over time due to surface diffusion. Also, at ohmic contacts you can get pits forming which can eventually degrade features.
Another issue is that at the size scales we're talking about, current insulators stop working. They're looking at switching to a variety of new materials for this purpose (for example, IrO2), but these are tricky. This is what they mean when they say "high dielectric constant" materials. Every MOS transistors has a this oxide layer (between the Metal and the Semiconductor), and that layer's thickness defines many of the physical properties of the device.
Finally, you have to worry about inductors to a lesser extent. Current inductors aren't quite good enough, but we're working on that too =) Nanoscale metallic alloys are definitely the way to go.
In any event, this article is sort of sensationalist (surprise!). I was able to make 20nm features using physical embossing (stamping metal liquid precursors with a plastic stamp and then curing them) back in 2002. Making features of small size scale is easy, it's keeping error rate, making interconnects, etc that's hard and annoying. Plasmonics is very neat though, I can imagine it working with time.
Besides, hard disks already have magnetic domains of ~ only a few nanometers anyway.
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Now my experience with electronics is quite brief at best, but I was under the impression that inductors were specifically avoided in electronic circuitry for a number of reasons, not the least of which is that they tend to be bulky. This is not a big problem because the effects of an inductor can be simulated wit
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They avoid them as much as possible, as you say. I meant by "lesser extent" that they aren't as big of a deal because we avoid them.
In rare situations they are necessary, and the limiting factor is one of standard magnetic materials ceasing to function as expected at very high frequencies. You wouldn't necessarily have them patterned into a circuit, but say for instance you want to use an inductor to transformer-couple AC signals into an analog to digital converter.
I have to reach a bit to find a real reaso
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Re:Fragility (Score:4, Funny)
A question for the physics people out there. At what point does Brownian motion become a serious consideration? What about tunneling electrons and other quantum-ish effects?
Depends on the fiber-content of the brownie...
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At what point does Brownian motion become a serious consideration?
I don't know about you, but after a few footlong chilidogs I take any Brownian motion very seriously.
Re:Plasmonic nanolithography? (Score:4, Insightful)
What exactly is the problem with this term? Just too "fancy" and "technical" for you salt of the earth Anonymous Cowards? It makes perfect sense if you know the root words for it, and it succinctly describes the technology:
- Plasmonic: Of or using plasmons. [wikipedia.org]
- Nano-: At the nanometer scale of operation
- Lithography: Lithography [wikipedia.org].
Maybe you can argue that the "nano" is superfluous, but it captures one of the two things that are significant about the new technique -- it uses plasmons instead of traditional light, and it can theoretically operate at a scale as small as 5-10 nm. ("Nano-" seems to be more significant, when you're at the point where you're talking single-digit nanometer resolution.)
Just because it's long and wordy doesn't mean that it's Star Trek nonsense. The phrase has a useful meaning.
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nanolithography? wtf, i just do *regular* lithography to get 300nm features... no wonder it's such a pain, we need a NANOlithography machine!
it does sounds awesome though, I'd give them money were I an MBA'd suit with no engineering experience!
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I don't even care what it does. Plasmonic nanolithography is just a freaking awesome name for something.
That's good... (Score:5, Funny)
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Impact on Big chip manufacturers (Score:3, Interesting)
It seems that they shrink their process at a fairly slow rate, and both companies seem to do it at about the same speed.
Also, if they both have been just advancing the standard techniques using high frequency light to etch all the chips, how easily could they change their manufacturing process over to something radically different?
Seeing chips with 100 times more density would offer incredible benefits for speed and power savings, seeing the recent changes that the 65nm to 45nm process has brought. Hopefully we'll actually be able to see this process being used inside the next 10 years though.
Re:Impact on Big chip manufacturers (Score:5, Informative)
Re:Impact on Big chip manufacturers (Score:4, Insightful)
A .sig comment:
I've always had trouble with this quote. "Last refuge" means, basically, "after trying all else, we do this."
Therefore, I would state that violence is the last refuge of the competent, and, generally, the first refuge of the incompetent.
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No, no. Obviously you didn't read the Foundation novels.
The quote means that the competent will always find solutions before resorting to violence, because for every possible situation there is an option better than violence. The incompetent can't find any of those options and use force, which is never the optimal solution.
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Obviously Asimov never had to contend with an armed robbery, rape, or violent assault before.
Short of dying/surrendering and taking a beating/willingly participating in the rape, violence is the only option.
Of course this could also be said as "Corollary: the above does not hold valid in the event of violence being in execution already."
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I think that it's meant to mean, 'if you find yourself in a situation where you feel you must use violence, you have been or are being incompetent'. In other words, you've either done something wrong in the past or you aren't seeing all your current options.
While I see your point, Asimov meant to take it even further. Your interpetation implies that violence can be an acceptable solution to a problem. Asimov is saying that it never is, and if you think it is a valid solution, you're not seeing the whole
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Filling one's belly involves violence, even if one is one of the strictest forms of vegan.
Therefore, either we're all incompetent because we all eat, or there's a flaw in Asimov's logic, which I rightly pointed out in the GP.
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If an economic or religious shutdown isn't violent, what is it, then? It most certainly is an exercise of force.
(Besides, we're talking about science fiction, here. If you can tell the future, of COURSE you're going to have an alternative to violence - it's like a rapist calling to set up a time and place for an appointment. The "Asimov" model here doesn't even come close to fitting realistic real-world scenarios because of this.)
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Perhaps this will make SSDs competitive now. You can get 4 GB microSD cards these days. If you could get j
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Physically, microSD is up to (at least) 8 GB these days:
http://www.newegg.com/Product/ProductList.aspx?Submit=ENE&N=2000070068%201053131144&name=Micro%20SDHC [newegg.com]
Of course, an SDHC card won't work in an SD reader, so there is room to argue about what is what.
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It seems that they shrink their process at a fairly slow rate, and both companies seem to do it at about the same speed.
I have no idea what definition of slow you're using at least. Making a new process work is absurdly complicated and expensive and they usually do it once every four years. By any standard I can think of the computer industry is still moving at breakneck speeds, setting new performance records, creating new device classes and entering new price brackets all the time. For older definitions of supercomputer, you're probably carrying one in your pocket. At this rate, it'll be a little chip under my watch in ten
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For older definitions of supercomputer, you're probably carrying one in your pocket. At this rate, it'll be a little chip under my watch in ten years.
You can already get mobile phone watches (CECT M800 and others), which have 2 Gigabytes of memory, have Bluetooth capability and which can both record and play mp3/mp4 files, along with using WAP internet access. There's even a watch with Wi-FI detection built in.
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That is why (well maybe a possible reason why) companies have just been making multi-core machine
Re:Impact on Big chip manufacturers (Score:5, Informative)
Do current chip manufacturers like Intel and AMD work on new lithography techniques, or do they focus more on architectural changes?
Yes. This research was funded by the National Science Foundation, a federal agency, but IBM, Intel, and AMD are all active in process technology research. I can't dig up much in the way of what they're currently researching, but here are a few things I was aware of in the past few years (and some things I dug while looking for them):
Some of the above research was about commercializing "pure" research done in independent labs like this experiment, but a lot of it was directly funded by the big fabrication companies and their clients and partners. Since I'm not in the fabrication industry myself, I can't really comment any further on who has done what (and how much each of the above deserves credit). This is just news I remember from years past.
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Intel is also on the forefront of photonic interconnects for Processors. HP just jumped on board a year or two ago. Often they fund university research and then try to implement it viably in CMOS or current fab processes.
Hybrid Si Laser by UCSB [intel.com]
Hooray for the Athlon64 X200! (Score:5, Funny)
Just think... we'll be able to have 198 cores doing nothing, now!
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It actually says nothing about whether or not these microprocessors would be able to operate faster.
But assuming this is real, it one of two things:
Maybe we'll have 200 cores which are about as fast as single cores we have now, in which case, nothing will be slower, and people who planned ahead (like Erlang developers) will find themselves running much faster. On top of that, embarrassingly parallel applications like raytracing will be that much more viable -- consider that it only took 16 cores to make a g
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All other things being equal, C or hand-optimized assembly will still be faster than Ruby or Python. Maybe the faster processors make the Ruby and Python "fast enough", but they still won't be as fast as hand-optimized assembly language o
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All other things being equal, C or hand-optimized assembly will still be faster than Ruby or Python.
True, and for some things, it will matter.
But take right now -- how many apps are Ruby or Python "too slow" for, on modern processors?
Of course that's ignoring the possibility of a big break through in interpreter and code generation technology before these chips come out.
It seems to be pretty steadily moving along. Just look at the recent JavaScript improvements.
Granted, none of these will be able to match hand-optimized assembly, by definition, because we can always output exactly the same program the compiler would (VM, runtime optimizations, and all), and additionally handle corner cases that the VM might be slower with.
But that distinctio
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I bet hand optimized assembly would still be faster (I do understand what you are driving at, but even on the 'garbage' available today, a huge swath of programming tasks are 'fast enough', even if implemented in something like Ruby or Python).
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I am making one assumption, though: That RAM keeps up. It would really suck to have 198 cores sitting idle, and the other two mostly just waiting for your RAM.
Presumably, as chips get faster, larger caches and more intelligent caching will become ever more important. Latency for main memory access really hasn't improved much from my first computer (Mac SE) to my current computer. Happily, though, the entire contents of my first computer's hard drive can now fit in 1% of my current computer's main memory, and the entire contents of my first computer's RAM easily fits within the on-chip cache.
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RAM is actually a good point... maybe they can put 16 tiny cores on the chip, and use the rest of the real estate for SRAM.
Isn't quantum effect the main problem now? (Score:3, Insightful)
I thought that the real problem now wasn't our ability to get feature sizes small, but rather that at those sizes, quantum effects really start to matter.
So how does being able to produce such small features really help us?
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Plasmonic? (Score:5, Funny)
Was this developed at the Gizmonic Institute?
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Another maskless scanning lithography system (Score:4, Informative)
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so this technology won't necessarily be as slow as electron-beam lithography, but I can't imagine it'll be cheap either.
You obviously didn't RTFA.
Modern 40/45nm and the upcoming 23nm chips need very short wavelengths to get produced.
This is expensive.
The new technique uses relatively long ultraviolet light wavelengths.
This is very cheap.
The researchers estimate that a lithography tool based upon their design could be developed at a small fraction of the cost of current lithography tools.
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Modern 40/45nm and the upcoming 23nm chips need very short wavelengths to get produced. This is expensive.
The new technique uses relatively long ultraviolet light wavelengths.
There's certainly a cost advantage to using longer-wavelength light for the exposure, but there's also a tradeoff in device complexity. Using longer-wavelength light for the exposure translates to cheaper lamps, mirrors, and optics, but the added complexity is going to add a lot of cost to the design and maintenance of these tools.
A conventional stepper performs a series of mechanical and optical alignments before exposing a die on the wafer, then steps to the next die to continue the process. A lithogra
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Its not that the interconnect isn't there, its just higher resistance. (for instance)
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This is very cheap.
The real question is how cheap. Current generation lithography systems have become ridiculously expensive. Preparing a mask for a 65nm process costs in excess of $2M. This makes short-run production at not-even-cutting-edge technology levels extremely expensive, and basically discourages smaller chipmakers from considering any niche applications that might require higher density.
Even if the production process is slower, if this can cut the initial preparation costs significantly, it co
Government funding (Score:5, Funny)
Nano-something you say? Can it possibly be used in the production of biofuels to increase homeland security against bioterrorism? If so I have a big check for you to pick up.
Terrabyte drives not enough? (Score:1, Offtopic)
I just had 2 fail over the weekend. I didn't lose anything vital because I had backups but everything I considered non-essential is gone (mostly just lots of VMWare images of various distros). At some point it beocmes a bitch to manage so much data.
Somewhat OT, but... (Score:1)
I just had 2 fail over the weekend. I didn't lose anything vital because I had backups but everything I considered non-essential is gone (mostly just lots of VMWare images of various distros). At some point it beocmes a bitch to manage so much data.
How old were they? I would have thought that drives young enough to be around that capacity would be nowhere near their MTBF*. Is this a reflection of a general decline in manufacturing standards? Are manufacturing standards decreasing with increased capacity? Or is there something else about these high capacity drives that reduces their reliability?
* Yes I understand that the M stands for mean and that some units fail earlier than most in order to make up that particular average. Still, a few years is
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I bought the system in June, so around 5 months old. One had a bad block. I pulled it out and when I powered back on the other one started ticking. I have no idea what happened? Static discharge? One drive affecting the other? Who knows. Anyway they're very well ventilated (2 large case fans sitting in front of the 4 drives. Their temp had never exceeded 40 degrees (usually around 28-32 when chugging along and sat at 25 idle with some variation depending on the weather). This machine is always on though.
Any
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Yeah they're damn convenient to have. I just hope reliability doesn't prove to be as bad as I suspect it will.
Overlay?? (Score:1)
Do they have a solution for controling overlay error between processing layers to less than 1.25nm?
If the answer is no, this technology is dead in the water as far as IC fabrication goes. (but may have very useful applications in other nanotech fields)
As someone who works in litho, I enjoy reading about any advances in resolution, but know that any advance in resolution must be accompanied by an even larger improvement in the non-insignificant task of placing each of the 10 to 50+ patterns needed to build a
Heh. (Score:1)
As usual, the industry thinks that Moore is better.
Gedankenexperiment (Score:2)
80 nm line width?
12 meters/second?
assume 5x5 mm die size
31250 80-nm lines spaced 80 nm apart can be laid on this die in one direction; twice that if the orthogonal direction is involved
each of these lines is 5 mm long, so their total length is 312.5 meters
at 12 m/s this will take 26 seconds per die
a 450-mm wafer, on the other hand, if treated as one big die, would take 31.5 minutes to cover in crossing lines.
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oops. forgot to carry the 2.
a 450-mm wafer would actually take 3.8 days to write
and that's for just two layers
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P.S. google this to get the answer
2 * sqrt( pi * ( 450 / 2 ) ^ 2 ) mm / 160 nm * sqrt( pi * ( 450 mm ) ^ 2 ) / 12 m/s
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Not that it matters, but that's off-topic, not flamebait.
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