ARM's Own Employees Complain About Anti-RISCV Website (theregister.co.uk) 89
lkcl writes: Phoronix and The Register have an insightful look into an effort by ARM that is reminiscent of Microsoft's "Get The Facts" campaign. RISC-V's design is a revamp of the RISC concept that is intended from the ground up to fix the mistakes and learn from the lessons of the past 30 years. Power efficiency is 40% better than ARM or Intel. Compressed instructions reduce I-cache misses by 20-25%, which is roughly comparable to the same performance that would be achieved by doubling the Instruction Cache size. Yet despite El Reg's insightful analysis,
all is not as it seems: on further investigation, some of ARM's criticism has merit, whilst some of it is clear out-and-out FUD from ARM that, being so critically dependent on free software, had its own employees complain so much that the site was pulled.
Also we cannot help but wonder which "Big Chip" company offered seven-figure salaries to try to shut down the IIT Madras Shakti Project. Most interesting however is the fact that ARM -- a $40 billion dollar company -- is rattled by RISC-V enough to use underhanded tactics, whilst Intel on the other hand is actually investing.
all is not as it seems: on further investigation, some of ARM's criticism has merit, whilst some of it is clear out-and-out FUD from ARM that, being so critically dependent on free software, had its own employees complain so much that the site was pulled.
Also we cannot help but wonder which "Big Chip" company offered seven-figure salaries to try to shut down the IIT Madras Shakti Project. Most interesting however is the fact that ARM -- a $40 billion dollar company -- is rattled by RISC-V enough to use underhanded tactics, whilst Intel on the other hand is actually investing.
Of course they are rattled (Score:2, Interesting)
They reality is that there has been very little innovation in the area of computer architecture in the past couple of years.
Only thing they have been doing is adding more cores.
Once you have a completely open CPU design that fabs can freely fabricate as much as they want, it will eat up a huge slice of the embedded extremely low power market.
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The next 10nm-based generation for Intel will have lower transistor performance than their refined 14nm++ and they freely admitted that (https://assets.pcmag.com/media/images/448825-10nm-technology-enhancements.jpg). If you have a Sky-/Kaby-/Coffee Lake the next ones are not going to be performance upgrades. And with the most recent Spectre-related issues (1.1 and 1.2) I don't expect any silicon fixes until at least Ice Lake in 2020.
Re:Of course they are rattled (Score:5, Interesting)
RISC-V is also an ISA (instruction set architecture) which is not an actual chip implementation. It's very similar to ARM in that it allows for companies to develop their own implementations of the chip, much like how Apple, Samsung, NVidia, and Qualcomm all make their own cores. The only difference is that RISC-V doesn't cost anything to license. You'll still need to pay chip designers to create an implementation if you don't have an open implementation that's free to use and there's no guarantee that any free implementation fits the use case that you'd want to target. Even if it does, there's still no guarantee that someone's proprietary implementation doesn't have such significantly better performance that it's better just to pay the additional cost anyway.
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There are ANN hardware designs wherein computer memory cells are integrated with the circuitry of artificial neurons, such as an LSTM neuron. Rather than a bunch of RAM and some program code, there's a bunch of flip-flop circuitry (RAM) built right into the neuron circuitry to create a fully-functional neuron package, along with supporting circuitry to allow programming by wiring those neurons inputs and outputs to each other how you like and writing or reading their values.
Theoretically, once you've pro
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Yea...... neurons aren't binary flip-flops.
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In his Turing Award lecture [iscaconf.org], David Patterson made a similar point that there is a big potential for domain-specific ICs. Google's TPU is an obvious example, but there are many other examples.
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Intel (Score:5, Insightful)
ARM is a technology company that makes all of it's money licensing it's IP. If people don't use ARM chips, they don't make money.
Intel is a chip manufacturing company. They have their own CPUs, but they have also manufactured ARM CPUs (XScale) and licensed their IP for other chip manufacturers to use. I don't think Intel particularly cares what CPUs they make, as long as they make money.
So, in the grand scheme of things, Intel probably wouldn't care about making RISC-V CPUs if they could make money doing so, whereas RISC-V is a direct threat to ARM's business model.
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Without it being king of low power, why choose ARM?
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I call hogwash on the claim that RISC-V is significantly more power efficient than ARM or Intel. I could not find the summary's claim of "Power efficiency is 40% better than ARM or Intel. " anywhere in the referenced material.
I'm guessing he's misquoting this line "instruction cache access alone dissipated 40% of the energy in a five-stage RISC pipeline."
Unless someone has come up with a RISC-V implementation that completely eliminates 100% of i-cache access power, in no way can you interpret that to mean R
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I've been programming ARM chips for the last 20 years, including on ARM-licensed cores on SoCs, and most of that time I have used the free GNU tools. Just like the RISC-V hardware is going to be good enough for most people, the same applies to free tools.
Another consideration is that the ARM core that we had licensed for our SoC came with the restriction that we were not allowed to modify the source code. Only the external interface could be modified, not the core itself. Obviously, the RISC-V core doesn'
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I don't know what color your glasses are, but the only "P-code/JIT technologies" that I'm aware of using ARM would be Android. And in that case, it would still take a lot of effort to port the whole system. The system is more than just the apps.
There's a lot more to ARM's market than things that run a Linux kernel, such as the entire Cortex M line. And those already tend to be fragmented by vendor because even with the same core, each vendor has its own flavor of peripheral units. In these applications, C
This summary is a mess (Score:5, Interesting)
I don't think I've ever read a more confusing summary. Clarifying that RISC-V isn't ARM's baby would have been a start. The subject of each sentence is also hard to decipher - is The Register's (do we have to call it "El Reg"? That's so twee) analysis about RISC-V, or about ARM's anti-RISC-V site? And so on.
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Oh yeah, and you fucked up one of the links.
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*sigh* it worked fine when i previewed it. https://groups.riscv.org/forum... [riscv.org] - i've emailed help@slashdot.org they should fix it soon enough
i wanted to provide lots for people to debate, rather than just "repeat someone else's story" like much of the internet "news" tends to be these days.
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I don't think I've ever read a more confusing summary.
So you missed Trump's take on the North Korea Summit?
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That's a non-sequitur.
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That says all you need to know about the average poster here.
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Oh, bugger off with the gatekeeping. Not everyone can be expected to know everything about everything. There's a reasonable level of explanation and this summary doesn't reach it. Should ARM need explaining to the Slashdot audience? No. Does RISC-V? Yes. It only takes a few words to lend the right amount of context.
And all that aside, basic rules of clarity should apply. The editors shoud have edited it to a higher standard.
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Ok. Since this is a tech site and according to your logic that means one should know everything about anything then please do the followinf:
Write a fast SATD function in assembly using the Risc-V vector extensions and make sure to thoroughly document and explain each line with comments to how each line relates to the SATD formula.
If you can't do this then kindly GTFO if you can't do something so basic.
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stop being retarded
Re:This summary is a mess (Score:4, Informative)
I don't think I've ever read a more confusing summary.
It might have helped if the first part of this had appeared on Slashdot. But yes, the summary, particular the title, is hopeless. A better title might be: "ARM beclowns itself with FUD against RISC-V"
This is about ARM FUD against RISC-V that appeared yesterday on a new site setup by ARM marketing creeps. It was a shock to people that respect ARM, so much so that some argued it was a hoax. It took some investigation [ycombinator.com] into the FUD site and its origins to convince people.
The fact is that what ARM sells is being commoditized. It's being commoditized because what they sell isn't all that novel any longer. The core of an ARM based integrated circuit is a small fraction of the value of these devices today; they real value is in the peripherals.
Of course they are (Score:1)
Re:I wonder why anyone cares at all (Score:5, Informative)
I have been reliably informed by slashdot that architectural differences don't matter at all because of something called a translation layer.
For modern, high performance cores like the latest x86's you may be right. With their billions of transistors, large multi-layer caches, out-of-order execution, pulling instructions apart into u-ops (and/or multitude of other tricks employed under the hood), some extra complexity in instruction decoding could be a minor part of the transistor budget. Changing little in terms of raw performance, power efficiency etc and making the CISC vs. RISC debate a moot point.
But that's not what RISC-V is about. It's a clean-slate architecture.
It's meant to scale. For a big high performance x86 a complex instruction set may not matter much, but if you're scaling down into low-power / low cost / embedded cpu's, a simpler ISA means smaller, cheaper, more power efficient devices. For scaling up, RISC-V provides for modular extensions to the instruction set. Making applications easy to move from low-end to higher-end parts (and vice versa). Or if you're into some many-core design, having a smaller / simpler core to start with, means you can put more of them on your slab of silicon.
If virtualization is your thing, RISC-V architecture is designed from the start with that in mind. Not bolted onto a 20~30 year old architecture.
Not to mention there's no IP royalties due should you want to bake your own IC's. For large-volume / thin-margin items, that could be a biggie even if you're talking a few $cents a pop (or thereabouts).
Surely the above isn't all - check the RISC-V website if you haven't already. Given the number of organizations & companies behind, I think it's set to take over a large share in several markets. Probably in the long term though, from the low end up.
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But that's not what RISC-V is about. It's a clean-slate architecture.
It should be noted that RISC-V also has a complicated decoder. "Compressed instructions" is just a soft way of saying it.
The downfall of RISC was in part because is lacked a complicated enough decoder to allow a dense enough code stream to enable the instruction fetcher to pipeline multiple operations per cycle. The old limited pentium U and V pipes were enough to blow DEC's Alpha out of the water, let alone where x86/x64 is today retiring 4 or more operations per cycle on well optimized code.
The RISC
Re:I wonder why anyone cares at all (Score:5, Informative)
It should be noted that RISC-V also has a complicated decoder. "Compressed instructions" is just a soft way of saying it.
The complexity of the RVC decoder and the complexity of an x86-64 decoder are nowhere near the same.
The x86-64 can have instructions from anywhere from 1 to 15 bytes long, and it takes a lot of processing to determine how long an instruction is, especially with all the prefixes (like the REX prefix that sees so much use in 64 bit code for x86). This necessitates a state machine of some sort to parse the prefixes and apply their modification to the effect of the instruction in question. Each instruction is highly encoded, which requires a complex decoder to determine the length and operands, before the actual performance optimizations like register renaming begin. Additionally, each variable-length instruction may be split into multiple micro-ops. Intel makes highly performant processors despite, not because of, the instruction set.
Unless you have non-standard extensions, RISC-V instructions can either be 2 or 4 bytes (the 2 byte ones being the compressed instruction set). Instructions must be 2-byte aligned. It is trivial to calculate the length of any instruction in such a chip - if the least significant 2 bits are 11, it's a 4 byte instruction, otherwise it's a 2 byte instruction. In 4 byte instructions, the source and destination registers, and the highest bit of the signed immedate are always stored in the same place in the instruction word, allowing register renaming to execute in parallel, to a large extent, with actually decoding the opcode. The 2 byte instructions are not quite as clean, but still much simpler to decode than x86. (See page 70 of the RISC-V user-level ISA documentation.) Additionally, it seems that every 2 byte instruction is equivalent to executing a certain 4 byte instruction. (p. 81)
And yet, apparently RISC-V compressed is more concise than most variable-length encodings. (Including x86-64, IIRC. So much for "x86-64 uses memory bandwidth and cache more efficiently.")
Source for the RISC-V compressed instruction formats starts at page 67. [riscv.org]
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RISC-V will probably never have performance even approaching x86. There is a lot to like about it, but you won't be seeing it used for high performance applications like games consoles or workstation CPUs.
The main reason is that the RISC concept itself turned out to offer much less flexibility for making optimizations on the CPU. A modern x86 CPU treats the x86 instructions as a kind of intermediate language that it dynamically translates into microcode operations on the fly, doing massive optimization in t
My Thoughts (Score:5, Interesting)
Of course Intel is investing (Score:2, Interesting)
All this time they've been living from the x86 architecture. Their last significant architecture change was Sandybridge, concocted in Israel rather than Intel headquarters. Now they have Spectre and Meltdown and AMD is running circles around them with Ryzen. They killed off Alpha by hooking HP on Itanium and then killing off Itanium. MIPS died from a culture of binary distribution/compatibility (simulating non-interlocking 3-stage pipelines with half-interlocking 7-stage pipelines is just absurd). ARM
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Please attempt to develop English language abilities expected of a high school freshman before trying to be cute with things like "El Reg."
Really. This is absurd.
it's what they call themselves! and i lurnd inglish from bwainiac https://google.com/search?q=br... [google.com]"i+can+do+science"
https://en.wikipedia.org/wiki/... [wikipedia.org]
https://google.com/search?q= [google.com]"el+reg"
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Hey guys, this is probably in rupees. So, 5-6 figure salary in dollars.
Still, hats off to the guy for turning down a large pay hike.
i couldn't put it in the main article, but i spoke to Madhu back in november, and it was USD $24 million. i still won't say who the company was but you can guess easily. and yes, turning down that much money is extremely brave. basically he realised that he could either be another PhD in amongst 100 other PhDs, or he could go back to his country and help his citizens reclaim sovereignty over their computing devices. when you're faced with that kind of decision it's not really a choice that you can walk
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i couldn't put it in the main article, but i spoke to Madhu back in november, and it was USD $24 million.
Luke that number is preposterous. Brian Krzanich never even received that much. Also it is a little misleading to characterize GS. Madhusudan as "another PhD in amongst 100 other PhDs". He is the one of the leaders of India's homegrown semiconductor movement.
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i couldn't put it in the main article, but i spoke to Madhu back in november, and it was USD $24 million.
Luke that number is preposterous.
then that gives you some idea of how much of a threat A... err... the unnamed company that tried to bribe^Whire their engineers.
Brian Krzanich never even received that much.
Also it is a little misleading to characterize GS. Madhusudan as "another PhD in amongst 100 other PhDs". He is the one of the leaders of India's homegrown semiconductor movement.
my understanding was that it was neel who received the "offer", but i can't be sure. ahh.... yes it was. ohhh that's reeeallly interesting. fuckers who published the article REMOVED the bit about neel's "offer"... and "the author of the article no longer works with us". mmmm rrriiiight....
https://web.archive.org/web/20... [archive.org]
"Some of that open source zeal can be seen in the Shakti team here. Gala, who was offered a ‘good seven digit package’ by one of the big chip giants, decided against it. “This was an interview over a cup of coffee. The moment of realisation for me was sitting in the cafeteria, and seeing a hundred other PhDs there. The only distinction I had over them was Shakti. If I left it, I would just be another ball in the bag. So that’s why I didn’t leave,” he says."
Power of techies. (Score:1)
Sources for RISC-V speculation? (Score:1)
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Luke could you provide sources for your claim that "some of ARM's criticism has merit?". The link provided is to your own mailing list post. I have been following RISC-V closely, and I'm curious what the "systemic failures" you describe there are.
*sigh* that's difficult to do, to provide "independent" sources, as no fucker is brave enough to put their neck on the line and stand up to them. the only reason i can publicly hold them accountable is because:
(a) i'm used to challenging people (and getting banned and censored and then predictably 100% so far seeing the project fail or fork or undergo a major change in leadership within 6-18 months)
(b) i'm not affiiated with a university, so do not have a "tenure" that could be threatened
(c) i do not work
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(b) i'm not affiiated with a university, so do not have a "tenure" that could be threatened
I believe the purpose of tenure is to grant academic freedom to the researcher. I don't see how criticizing RISC-V would "threaten" a tenured position.
over the years i've read enough to be able to watch for the signs, and to give people the opportunity to sort things out for themselves... if they so wish. the six Systemic Laws of Organisations listed in "Invisible Dynamics" is one of the best guides i know. any one of those Systemic Laws gets violated, an organisation is guaranteed to be in trouble. *fixable* trouble... if they choose, but still trouble nonetheless.
Do you know of any online reference to these "systemic laws?" If these laws are reasonable, I'd like to perform my own analysis of the RISC-V community's stability. If there aren't any references online, would you mind briefly outlining what the six laws are?
this despite trying to warn them that the Shakti Foundation is backed by UNLIMITED resources from the Indian Government, and if the RISC-V Foundation doesn't get their act together they'll fork the entire RISC-V software and hardware eco-system, and over the next 5-10 years drop a hundred million completely incompatible processors onto the planet, causing *exactly* the scenario that ARM described in their now-offline website.
Hmmm, this does seem like a worst-case scenario, but I don't see any incentive for the Indian develope
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(b) i'm not affiiated with a university, so do not have a "tenure" that could be threatened
I believe the purpose of tenure is to grant academic freedom to the researcher. I don't see how criticizing RISC-V would "threaten" a tenured position.
whilst i am well-known (even myself) for not known for getting things totally accurate, i'm sure you know what i mean: a student or professor publicly criticising a highly-respected person... for example david patterson to pick one hypothetical name, would raise... a lot of eyebrows.
over the years i've read enough to be able to watch for the signs, and to give people the opportunity to sort things out for themselves... if they so wish. the six Systemic Laws of Organisations listed in "Invisible Dynamics" is one of the best guides i know. any one of those Systemic Laws gets violated, an organisation is guaranteed to be in trouble. *fixable* trouble... if they choose, but still trouble nonetheless.
Do you know of any online reference to these "systemic laws?" If these laws are reasonable, I'd like to perform my own analysis of the RISC-V community's stability. If there aren't any references online, would you mind briefly outlining what the six laws are?
the book's available on amazon, my copy's in storage and i really wish it wasn't. it costs quite a lot to replace https://www.amazon.co.uk/Invis... [amazon.co.uk]
as i can best recall them they are listed on page 23 with their associated "anti-
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whilst i am well-known (even myself) for not known for getting things totally accurate, i'm sure you know what i mean: a student or professor publicly criticising a highly-respected person... for example david patterson to pick one hypothetical name, would raise... a lot of eyebrows.
Isn't this a general criticism of any democratic system? It would raise a lot of eyebrows because one would expect that the authority figure is qualified in making his/her judgements. I'm still not sure what the issue is here.
hilariously a lot of them are the subject of Dilbert strips. CEOs telling you that "everything's well" (when it clearly isn't) has an *extremely* damaging effect as it completely locks up the *entire* company.
"Don't be Dilbert" seems to be a good mantra to follow.
it does if i am helping them to create a mobile-class processor, that goes into smartphones, tablets, netbooks and chromebooks, which, due to their reduced cost due to huge volume, result in them being sold out of india on amazon, making their way world-wide, and people find that they're not DRM-locked and that they can quite easily replace the OS right down to the bedrock.
the problem will come when they find that the standard debian-riscv and standard fedora-riscv distros.... don't work. they'll then start investigating and find that they need a complete total hard forked version of debian, fedora and so on. at that point it becomes hell for the debian and fedora maintainers, who are pretty much guaranteed to be swamped with requests for support of such low-cost low-power hardware.
What is the motivation for the Shakti engineers to deviate so far from the base ISA that their hardware will no longer be compatible with the general ecosystem? Also, I still don't understand how any of these criticisms are due to
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whilst i am well-known (even myself) for not known for getting things totally accurate, i'm sure you know what i mean: a student or professor publicly criticising a highly-respected person... for example david patterson to pick one hypothetical name, would raise... a lot of eyebrows.
Isn't this a general criticism of any democratic system? It would raise a lot of eyebrows because one would expect that the authority figure is qualified in making his/her judgements.
eeexactlyyyy. and unfortunately, we are talking about people who, by virtue of being professors, are used to teaching, used to being always right, and used *never* to being questioned. and, indeed, *in their area of expertise*, they are almost 100% right, 100% of the time. this is an example of the systemic law "respect expertise, respect length-of-service".
unfortunately there are two (quite different but related areas) where this becomes a problem:
(1) when the experienced and long-standing expert encoun
What were they thinking? (Score:2)
What where they even thinking to launch a smear site like that? It's certain to backfire: the message such a site gives is that RISC-V is a serious challenger to ARM, if ARM has to go out and smear it, and people who've never even heard of RISC-V will now be checking it out because this kind of story gets picked up by the computing press and gives a huge amount of free publicity to RISC-V.
Much ado about nothing (Score:2)
Am I the only one who actually read the archived web site [archive.org] and figured their talking points were pretty benign and reasonable? I mean, RISC-V isn't even a full spec at the moment and is still a work in progress.
Like most things I've come across in the open-source world, RISC-V is a bunch of good ideas, but ARM has proven, working implementations of their own ISA. From a business perspective, it's not outlandish to boast about that. If ARM were tearing apart the concepts behind RISC-V, then that would be a