New UCIe Chiplet Standard Supported by Intel, AMD and Arm (anandtech.com) 20
A number of industry stalwarts including Intel, AMD, Arm, TSMC, and Samsung on Wednesday introduced a new Universal Chiplet Interconnect Express (UCIe) consortium. AnandTech: Taking significant inspiration from the very successful PCI-Express playbook, with UCIe the involved firms are creating a standard for connecting chiplets, with the goal of having a single set of standards that not only simplify the process for all involved, but lead the way towards full interoperability between chiplets from different manufacturers, allowing chips to mix-and-match chiplets as chip makers see fit. In other words, to make a complete and compatible ecosystem out of chiplets, much like today's ecosystem for PCIe-based expansion cards.
The comparisons to PCIe are apt on multiple levels, and this is perhaps the best way to quickly understand the UCIe group's goals. Not only is the new standard being made available in an open fashion, but the companies involved will be establishing a formal consortium group later this year to administer UCIe and further develop it. Meanwhile from a general technology perspective, the use of chiplets is the latest step in the continual consolidation of integrated circuits, as smaller and smaller transistors have allowed more and more functionality to be brought on-chip. In essence, features that have been on an expansion card or separate chip up until now are starting to make their way on to the chip/SoC itself. So like PCIe moderates how these parts work together as expansion cards, a new standard has become needed to moderate how these parts should work together as chiplets.
The comparisons to PCIe are apt on multiple levels, and this is perhaps the best way to quickly understand the UCIe group's goals. Not only is the new standard being made available in an open fashion, but the companies involved will be establishing a formal consortium group later this year to administer UCIe and further develop it. Meanwhile from a general technology perspective, the use of chiplets is the latest step in the continual consolidation of integrated circuits, as smaller and smaller transistors have allowed more and more functionality to be brought on-chip. In essence, features that have been on an expansion card or separate chip up until now are starting to make their way on to the chip/SoC itself. So like PCIe moderates how these parts work together as expansion cards, a new standard has become needed to moderate how these parts should work together as chiplets.
So, are they going to charge royalties? (Score:2)
Now, are they going to charge royalties?
And / or, do you need to be a member of their consortium to use this technology & standard?
Inquiring minds want to know, (okay, barely curious single mind).
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I think it would probably have taken less time for you to read the entire summary (hint: Ctrl + S and type "open" to get your answer), than to make your post.
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Yes but no. (Score:2)
lead the way towards full interoperability between chiplets from different manufacturers, allowing chips to mix-and-match chiplets as chip makers see fit.
While the standard may allow mix and match, nothing is going to change on the consumer side. Intel and AMD will still require different motherboards and different sockets. What this does is reduce the number of components that motherboard manufacturers need to be changed when switching between making and AMD motherboard and an Intel motherboard. This will reduce the design costs as well as component design costs. Will you see a dime from these cost reductions? Doubtful.
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Will you see a dime from these cost reductions? Doubtful.
Often these kinds of cost reductions mean the price doesn't increase (or as much) and so the consumer may well see a discount but it's a less obvious one.
Re:Yes but no. (Score:4, Informative)
Actually none of that is true. UCIe is only for chiplets. Chiplets are sub-chips on a chip package - so think of it more like the Pentium Pro which had a processor die and a cache die built into a single package. But here the package may contain multiple dies and the UCIe standard allows different manufacturers to build chiplets that get integrated into one final chip. So instead of AMD having to have a special die made for say, DDR5 memory controllers that only talks to the AMD chip through the interface, AMD will build a UCIe interface and the memory controller chiplet can use it to talk to the AMD chip. At the same time, Intel may decide to do the same thing, so both AMD and Intel could use the exact same UCIe memory controller without needing the memory controller manufacturer to design special AMD only parts or Intel only parts.
Of course, this can also lead to our friend Rambus (who are still around, amazingly enough) to do a UCIe controller to support their proprietary memory chips.
Basically it's a way to have a whole series of chips that have varying functionality and instead of having to do it on die, it can be populated as necessary. So AMD could have a UCIe GPU chiplet, and populate it with various options as needed - useful for laptops where the manufacturer might want a particular CPU and GPU combination, and AMD can easily supply it by putting the right GPU chiplet. If another one wants a different GPU, AMD only has to put the new GPU in for the manufacturer.
So AMD doesn't need to stock two CPUs with different GPUs on a single die (expensive) - they can stock a CPU core and two GPU dies, and build whatever CPU+GPU spec was desired.
Or say, for AMD's Threadripper, they could populate the bus controller and as many core chips they need - so instead of having 4 different configurations, they just build it as you want it since the cores chiplets are identical.
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This seems to be a chiplet interconnect.
I think this means it has nothing to do with the motherboard. It's all within the CPU package, so it should allow them a "standard way" to connect chiplets from different manufacturers. So someone can make an x86 core, with many ARM cores, with CUDA cores (assuming Nvidia is taking part in this) for ML, etc and make a "chip" to slot into an appropriate motherboard.
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The consumer has one perspective, but there are other parties involved. Even if it were true that nothing would change for consumers, this is still good news for engineers and investors.
"Chiplets" was a new term for me... (Score:2)
"A chiplet is a tiny integrated circuit that contains a well-defined subset of functionality. It is designed to be combined with other chiplets on an interposer in a single package." - https://en.wikipedia.org/wiki/... [wikipedia.org]
So basically fab separate sections of a complex part (better yields), then combine them before putting them into a single package. I'm honestly a little surprised that a standard between these people is useful or being worked on. Though I guess it depends where the functional boundaries are.
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It's a relatively new thing spearheaded mostly by AMD. Zen2 processors were already a chiplet design interconnected with infinity fabric to a central I/O core.
Here's an image of an 28 core Intel Xeon W-3125X https://cdn.mos.cms.futurecdn.... [futurecdn.net]
Compare that to an AMD Epyc-2 7000 something or other 32 core https://imgur.com/NNUy6Sa [imgur.com]
Or more commonly (and not direct links to images since some people don't like that):
An AMD Ryzen Zen 2 desktop CPU https://wccftech.com/amd-ryzen... [wccftech.com]
and an Intel i7 11700K https://wccft [wccftech.com]
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It's a relatively new thing spearheaded mostly by AMD.
If you're referring to renaming "MCM" as "chiplets", then yes. If you're referring to MCM or chiplets as a technology, then very much no.
POWER chips were MCM back in the 90s. Intel as well.
POWER5 (early 2000s) were multi-core "chiplets" (a la today's Zen procs), which are an interesting tradeoff in performance costs vs manufacturing costs (chiplets are necessarily NUMA, and that has a negative performance cost, but at the same time, being able to paste more cores onto a die is a lot cheaper than having t
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No MCM and Chiplets are different things**, though Chiplets by necessity are built as MCMs.
The POWER5 had autonomous cores in multiple chips with attached L3 cache as a separate chips all combined on one module. Each chip stands by itself and is feature complete. You can in theory reduce the CPU to just one chip (and its associated cache). Or you can expand it to 4 chips (and their associated cache).
The Zen2 by comparison has non-autonomous cores, they cannot operate by themselves and you don't get a CPU wi
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No MCM and Chiplets are different things**, though Chiplets by necessity are built as MCMs.
Says you.
The POWER5 had autonomous cores in multiple chips with attached L3 cache as a separate chips all combined on one module. Each chip stands by itself and is feature complete. You can in theory reduce the CPU to just one chip (and its associated cache). Or you can expand it to 4 chips (and their associated cache).
Wait, do you think those cores weren't interconnected? lol.
You can reduce a Zen3 chip to a single I/O block and CPU cluster.
As such, you can't simply disconnect a POWER core from its cache die.
The fact that in POWER5 days, it was still common practice to put the bus peripherals off-cpu doesn't negate the fact that these are the same thing.
The Zen2 by comparison has non-autonomous cores, they cannot operate by themselves and you don't get a CPU with just the CCX (core complex) by itself. That's the basis of the Chiplet design, that functional limited purpose tasks are relegated to a separate chiplet, in this case the I/O and MMU which are independent and shared by the CCXs.
That's hardly relevant, especially to the context of UCIe.
** AMD's marketing department hasn't helped this as they've often referred to the CCXs as "chiplets" in which case that would agree with what you're saying, but their technical documents as well as the papers articles on chiplet design by AMD and Intel published on IEEE are very clear that the definition of a chiplet is a special purpose minimum scope chip, not an autonomous CPU core classically thrown together on MCMs.
They really haven't helped this, since they referred to chiplets as MCM [techpowerup.com] before they coined the word "
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Or, here's the sauce right from the horse's mouth [amd.com]
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Says you.
Err no, says Intel, AMD and the engineering community. Go read some papers on this, don't come complaining to me about the definition being used in industry. I'm not in control of it.
Wait, do you think those cores weren't interconnected? lol.
Sorry I'm out. It's clear you're not reading or actively purposefully pretending to not understand the post I made. Try again, and come back to me ideally after you look at an architectural diagram of both products. After all, if you don't want to understand words, maybe pretty pictures are more on your level.
I'm out. Happy wee
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Err no, says Intel, AMD and the engineering community. Go read some papers on this, don't come complaining to me about the definition being used in industry. I'm not in control of it.
Intel has adopted the use of the word chiplet- why wouldn't they? It's a great fucking word.
I am an engineer, and thus belong to "The engineering community".
Feel free to cite a paper. For every paper you cite that discusses "chiplets", I will demonstrate how it's not a new idea in form or theory.
Sorry I'm out. It's clear you're not reading or actively purposefully pretending to not understand the post I made. Try again, and come back to me ideally after you look at an architectural diagram of both products. After all, if you don't want to understand words, maybe pretty pictures are more on your level.
Nice cop-out.
I'm very familiar with the architecture of both products, which is why I mentioned them.
The POWER5 contains a core complex and a cache complex. These are all connected via interconnect to an off-pa
Miniaturization (Score:2)
My guess is that this will ultimately result in a substantial reduction in the size of quite a bit of equipment that currently requires several much larger discrete components. Lots of things that currently occupy substantial circuit board space will turn into chiplets that are contained in a little can on a board.