TSMC Unveils 1.6nm Process Technology With Backside Power Delivery

An anonymous reader quotes a report from Tom's Hardware: TSMC announced its leading-edge 1.6nm-class process technology today, a new A16 manufacturing process that will be the company's first Angstrom-class production node and promises to outperform its predecessor, N2P, by a significant margin. The technology's most important innovation will be its backside power delivery network (BSPDN). Just like TSMC's 2nm-class nodes (N2, N2P, and N2X), the company's 1.6nm-class fabrication process will rely on gate-all-around (GAA) nanosheet transistors, but unlike the current and next-generation nodes, this one uses backside power delivery dubbed Super Power Rail. Transistor and BSPDN innovations enable tangible performance and efficiency improvements compared to TSMC's N2P: the new node promises an up to 10% higher clock rate at the same voltage and a 15%-20% lower power consumption at the same frequency and complexity. In addition, the new technology could enable 7%-10% higher transistor density, depending on the actual design.

The most important innovation of TSMC's A16 process, which was unveiled at the company's North American Technology Symposium 2024, is the introduction of the Super Power Rail (SPR), a sophisticated backside power delivery network (BSPDN). This technology is tailored specifically for AI and HPC processors that tend to have both complex signal wiring and dense power delivery networks. Backside power delivery will be implemented into many upcoming process technologies as it allows for an increase in transistor density and improved power delivery, which affects performance. Meanwhile, there are several ways to implement a BSPDN. TSMC's Super Power Rail plugs the backside power delivery network to each transistor's source and drain using a special contact that also reduces resistance to get the maximum performance and power efficiency possible. From a production perspective, this is one of the most complex BSPDN implementations and is more complex than Intel's Power Via. Volume production of A16 is slated for the second half of 2026. "Therefore, actual A16-made products will likely debut in 2027," notes the report. "This timeline positions A16 to potentially compete with Intel's 14A node, which will be Intel's most advanced node at the time."

Backside!

[glowworm]

Ideal when you need some power in your backside! But it it less burny to your derriere than Carolina Reapers?

Re:Backside!

[DrMrLordX]

You totally whiffed on the opportunity for "power bottom" jokes.

Re:

[flyingfsck]

Intel is so far behind the curve, they will never catch up with the Chinese.

Re:

[ShanghaiBill]

Intel is so far behind the curve

The past decade has made it clear that being both a chip designer and a chip fabber is a bad idea. You are only as strong as the weakest link.

Almost all of Intel's competitors have gone fabless and benefited from that.

Samsung is the only other big company that does both design and fabbing.

Re: Backside!

[BytePusher]

In a year or two you'll be saying the opposite when fabs price gouge the designers. By then it'll be disruptive to have both design and fab in one house.

Re:Backside!

[necro81]

Intel is so far behind the curve

Intel also has backside power delivery for their latest nodes. Here's IEEE Spectrum reporting on it [ieee.org] from June 2023

Re:

[stabiesoft]

Thanks, nice link. Not sure if they will/did make it, but the article says 2024 for production. The submission indicates TSMC will be a couple years later for their backside power.

Re:

[boulat]

Intel is not competing with the Chinese, because Taiwan is not China.

Rate of progress

[SysDaemon]

The first chip I designed was based on a 2 micron gate array process. Initial parts were laser-exposed resist, stepped on an x-y table, yeah Swiss company 37 years ago...

Re: Rate of progress

[bradley13]

Yeah, it's pretty crazy. I also did EE a few decades ago, and the modern tech is astounding. Not too far from individual atoms playing significant roles.

Re: Rate of progress

[bill_mcgonigle]

Make sure you understand that these sub-28-nm claims are "equivalent" made by stacking and layering.

The feature size on a "7nm" could be 28nm but they stack four of them and Marketing says "as if 7nm".

Soon they will advertise processes /smaller/ than atoms. Not even kidding.

Re:

[smoot123]

The first chip I designed was based on a 2 micron gate array process. Initial parts were laser-exposed resist, stepped on an x-y table, yeah Swiss company 37 years ago...

"I remember when gate widths were measured in microns." Tell me you're old without saying you're old.

Gather 'round kids. I worked at HP when PA-RISC was just releasing (this was late '80s). The very first systems were built using discrete TTL chips (intended for lab use but a few got shipped to customers anyway). Integrated CPUs were imminent. The processor guys used a code shorthand to talk about upcoming systems: the PN7 was a processor built using NMOS with a 7 micron gate. One of our tech leads joked th

Re:

[dsgrntlxmply]

Early designs were knife cut into Rubylith masking (stripping) film then photoreduced. If I recall correctly, I was shown an example during a tour of Zilog in the Z80 era. I hand cut simple hobby PCB designs into the similar Amberlith film. These mechanical films were used in traditional graphic arts prepress. The Los Angeles Times job classifieds had ads for "Experienced strippers", and not THAT kind. 1.6 nm is down to counting atoms on fingers and toes.

Re:

[tlhIngan]

Early designs were knife cut into Rubylith masking (stripping) film then photoreduced. If I recall correctly, I was shown an example during a tour of Zilog in the Z80 era. I hand cut simple hobby PCB designs into the similar Amberlith film. These mechanical films were used in traditional graphic arts prepress. The Los Angeles Times job classifieds had ads for "Experienced strippers", and not THAT kind. 1.6 nm is down to counting atoms on fingers and toes.

For those not in the know, Rubylith and Amberlith wer

So When Can I Get My 8Ghz AMD Chip?

[zenlessyank]

Hopefully it will only use 65 watts and can address 24 TB of RAM.

Re:

[phantomfive]

I was hoping we'd make it to 20 Ghz before Moore's law failed. Oh well.

Re:

[zenlessyank]

We still have the pico's to go.

Re: So When Can I Get My 8Ghz AMD Chip?

[beelsebob]

Moores law says nothing about the speed you can run the transistors at. Only how many you can fit onto a given area for a unit price.

Re:

[phantomfive]

Yes. And yet, I was hoping we'd make it to 20 Ghz before Moore's law failed. Oh well.

Re: So When Can I Get My 8Ghz AMD Chip?

[BytePusher]

Someone correct me if I'm wrong, but addressing 24 TB if memory should be possible with any 64 bit CPU. The limit is usually the board the CPU is attached to and what memory chips are feasible at the time to wire into the board.

Re: So When Can I Get My 8Ghz AMD Chip?

[ThurstonMoore]

X64 requires a minimum of 48 bit addressing which allows up to 256TB of memory.

What what

[Ryanrule]

In the ?

Re:

[flyingfsck]

No, no. In the ;

Backside Power Delivery

[Anonymous Coward]

Backside Power Delivery

Awwww ... for a moment there I thought it said 'Backside Porn Delivery' ...

Nice

[Fons_de_spons]

Worked in chip design company once. It was a running joke whenever someone was telling that we needed more silicon area. Just put it on the back. It made newbees think. Some would run off with the idea. Good brain exercise. Guess one of the newbees put through and made it work.

Re:

[necro81]

...we needed more silicon area. Just put it on the back...

In this case it's less about silicon area and more about metal area.

Re: Nice

[Fons_de_spons]

Well... it depends area can be constrained by a lot.

Re:

[q_e_t]

Bite TSMC's shiny metal ass?

Incremental

[backslashdot]

Moore's law has collapsed/failed. In the 1980s and 1990s the processing power would DOUBLE every 18 months and costs would reduce. Now we're only getting 10 to 20% improvements and costs increase .. .. that's fucking lame.

Re:

[mistergrumpy]

Not too suprising. Not only was the processing power doubling, so was the cost of building a fab. Anything undergoing exponential growth/improvement will hit a wall sometime.

Re:Incremental

[Misagon]

Moore's law is over because we have reached the physical limits of silicon. A gate is only so many number of atoms across now, and leakage currents are becoming an issue.

Instead of fitting smaller transistors next to each other, transistors are now more vertical.
The "nm" and "Ångström" figures used now do not depict the real density of the process. It is an equivalent to what the density would have been if they had been able to shrink the conventional process even further.

Backside power delivery and stacked chiplets are also ways to grow vertically instead of horizontally.

Re:

[necro81]

Moore's law has collapsed/failed. In the 1980s and 1990s the processing power would DOUBLE every 18 months and costs would reduce. Now we're only getting 10 to 20% improvements and costs increase .. .. that's fucking lame

Well, by all means jump in and show us how it's supposed to be done!

Gordon Moore himself has always been lukewarm about the eponymous "law". It never was a law: it was a backward-looking statement about about transistor density in the 1960s, with some speculation about trends for the

Re:

[smoot123]

Moore's law has collapsed/failed. In the 1980s and 1990s the processing power would DOUBLE every 18 months and costs would reduce. Now we're only getting 10 to 20% improvements and costs increase .. .. that's fucking lame.

Ummm, you do realize a 10-20% quality increase every year is astounding in any other industry, right? What would it be like if books got 15% better every year?

If you take a more expansive view of performance, I wonder how well Moore's Law holds up. From what I heard, storage has been increasing in capacity at higher than Moore's Law rates. I think we were seeing doubling in 18 months, not 24. A crusty old dinosaur I worked with told me of when the entire storage industry was 5 petabytes a year. Now a petaby

Re:

[q_e_t]

There's a story involving a chess board and doubling...

Once again...

[Rei]

Taiwan reinforces its silicon shield.

not GHz, Knots

[bugs2squash]

These chips must be huge if the feature size is 1.6 nautical miles.

Re:

[q_e_t]

Yeah, you'd need a computer the size of a planet. By the way, has anyone seen any dolphins recently?