HP to embed EPIC and more AMD details

In a very interesting twist, HP has announced that it will be using techniques it developed for EPIC for use in embedded systems: HP claims that the compilation techniques required by EPIC to make parellelism explicit in critical code paths can be used to create a custom hardware engine with sufficient hardware parallelism to meet the performance requirements of the application. If this were to be done automatically (by a compiler), HP would have a killer product that could explain their motivation for working with Intel on EPIC technology (it was originally HP's idea): HP has been focussing more on Embedded systems recently (witness their recent spat with Sun over their embedded Java) and with the workstation and PC markets becoming saturated this may be a very lucrative move on their part).

In an update to our previous article, AMD has revealed more details about its K7: rather than using RISC operations, the K7 uses MacroOps -- 15 byte bundles of instructions able to encode up to 2 primitive X86 instructions. The instruction decode unit serves up to 3 MacroOps per cycle (6 instructions at most). To reduce stalls, up to 15 MacroOps can be buffered and rescheduled before hitting one of the K7's three integer pipes: apparently this increases the amount of paralellism the K7 can uncover and exploit. The FPU's instruction buffer is even deeper at 44 entries. However the price of all of this is a huge die: 184 sq mm of silicon and the associated costs in decreased yields. Don't expect cheap K7s for a while.